PEX 8696-AA50BC F PLX Technology, PEX 8696-AA50BC F Datasheet - Page 4

• Manufacturer Part Number: PEX 8696-AA50BC F
• Description: Peripheral Drivers & Components (PCIs) 96Ln/24Pt PCI Exprss Gen 2 (5 GT/s) Swtch
• Manufacturer: PLX Technology

Specifications of PEX 8696-AA50BC F

• Mounting Style: SMD/SMT
• Propagation Delay Time: 176 ns
• Package / Case: HFCBGA-1156
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

variety of host-centric applications. Figure 6 shows a
server design where, in a quad or multi processor
system, users can assign endpoints/slots to CPU cores to
distribute the system load. The packets directed to
different CPUs will go to different (user assigned) PEX
8696 upstream ports, allowing better queuing and load
balancing capability for higher performance.
Multi-Host Systems
In multi-host mode, the PEX 8696 can support up to
eight hosts at once. By creating eight virtual switches,
the PEX 8696 allows eight hosts to fan-out to their
respective endpoints. This reduces the number of
switches required for fan-out, saving precious board
space and power. In Figure 7, the PEX 8696 is being
shared by six different CPU cores (hosts) on three
servers, with each CPU core running its own
applications (I/Os). The PEX 8696 assigns the endpoints
to the appropriate host and isolates them from the other
hosts. In Figure 7, the endpoints are assigned to the CPU
core of the same color.
High-End Graphics Systems
The PEX 8696’s 96 lanes can come in handy for high-
end graphics systems, such as high-resolution gaming
and medical imaging applications, employing two or
more GPUs alongside multiple endpoints. Figure 8a
shows a dual-graphics system where the PEX 8696 is
being used to fan-out to two GPUs using x16 links and
numerous (up to 16) endpoints using x4 and x8 links.
Figure 8b, shows an ultra-gaming system using the PEX
© PLX Technology, www.plxtech.com
Figure 6. Host Centric Dual Upstream
Figure 7. Multi-Host System
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
I/O
CPU
Chip
Chip
Set
Set
I/O
CPU
x4
I/O
x16
PCIe Gen1 or PCIe Gen2 slots
x8s
PEX 8696
Chipset
Chipset
Chipset
Chipset
PEX 8696
CPU
CPU
CPU
CPU
I/O
I/O
I/O
CPU
Chip
Chip
PEX 8696
PEX 8696
PEX 8696
PEX 8696
Set
Set
I/O
I/O
I/O
CPU
CPU
CPU
CPU
x8
CPU
I/O
I/O
I/O
x8
I/O
I/O
I/O
CPU
Chip
Chip
Set
Set
I/O
I/O
I/O
Memory
Memory
Memory
Memory
CPU
I/O
I/O
I/O
PEX 8696, PCI Express Gen 2 Switch, 96 Lanes, 24 Ports
x4s
Page 4 of 4
8696 to fan-out to four GPUs via x16 links. In both
examples, two x16 upstream ports are being used. Using
PEX 8696’s multi-host capabilities, two separate virtual
hierarchies can be created, assigning GPUs & endpoints
to a particular CPU core via the x16 upstream ports.
Host Failover
The PEX 8696 can also be utilized in applications where
host failover is required. In the below application
(Figure 9), two hosts may be active simultaneously and
controlling their own domains while exchange status
information through doorbell registers or I
The devices can be programmed to trigger fail-over if
the heartbeat information is not provided. In the event of
a failure, the surviving device will reset the endpoints
connected to the failing CPU and enumerate them in its
own domain without impacting the operation of
endpoints already in its domain.
GPU
GPU
GPU
GPU
GPU
GPU
GPU
GPU
Figure 8a. Dual-Graphics System
x16s
I/O
I/O
I/O
I/O
Figure 9. Host Fail-Over
I/O
I/O
I/O
I/O
x8
PEX 8696
PEX 8696
PEX 8696
PEX 8696
Chipset
Chipset
Chipset
Chipset
PEX 8696
PEX 8696
PEX 8696
PEX 8696
CPU
CPU
CPU
CPU
CPU
CPU
Chip
Chip
Set
Set
CPU
CPU
CPU
CPU
CPU
CPU
x16s
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
x4s
& x8s
x4 & x8
x8s
Figure 8b. Ultra-Gaming System
Chipset
Chipset
Chipset
Chipset
CPU
CPU
CPU
CPU
PEX 8696
PEX 8696
PEX 8696
PEX 8696
GPU
GPU
GPU
GPU
PEX 8696
PEX 8696
PEX 8696
PEX 8696
GPU
GPU
GPU
GPU
CPU
CPU
CPU
CPU
CPU
CPU
Chip
Chip
Set
Set
x8
5/14/2009, Version 1.1
GPU
GPU
GPU
GPU
CPU
CPU
x16s
GPU
GPU
GPU
GPU
2
C interface.
x16s