MAX1441GUP/V+ Maxim Integrated Products, MAX1441GUP/V+ Datasheet - Page 20
MAX1441GUP/V+
Manufacturer Part Number
MAX1441GUP/V+
Description
Touch Screen Converters & Controllers PROXIMITY SENSR el Proximity and Tou
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX1441GUPV.pdf
(41 pages)
Specifications of MAX1441GUP/V+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Automotive, Two-Channel Proximity and
Touch Sensor
Table 5. Special-Purpose Register Bit Description (continued)
Table 6. Special-Function Register Map Section I
Table 7. Special-Function Register Map Section II
Table 8. Special-Function Register Map (Section III)
All peripherals and operations that are not explicit
instructions in the device are controlled using special-
function registers (SFRs). These registers allow commu-
nication and data exchange between the CPU and the
peripherals. Normally, interaction between a peripheral
20
DP0 (03h, 0Fh)
Initialization
Read/Write Access
DP0[15:0]
M[x] SPECIFIER 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
M0
M1
M2
M3
M4
M5
M[x]
M[x]
M0
M1
M2
M3
M4
M5
M0
M1
M2
M3
M4
M5
MODULE
MODULE
REGISTER
MODULE
00000
00001
00010
00011
00100
00101
SPECIFIER
SPECIFIER
00000
00001
00010
00011
00100
00101
00000
00001
00010
00011
00100
00101
CO1
—
—
—
—
—
AFEINTST
Special-Function Registers
00000
Data Pointer 0 (16-Bit Register)
This register is cleared to 0000h on all forms of reset.
Unrestricted read/write.
Data Pointer 0 Bits [15:0]. This register contains the data address for data memory access. The
contents of DP0 can be automatically incremented/decremented for read/write data-memory operation.
PO0
CO2
CRSLT1L
—
—
—
—
—
—
—
—
—
01000
PI0
—
—
—
—
DSB
—
—
—
—
—
00001
EIF0
SCT
SSB2 AFEIE
—
—
—
—
—
—
—
—
—
CRSLT1H
01001
PD0
—
—
—
—
INDEX OF SPECIAL-FUNCTION REGISTER (SECTION III)
INDEX OF SPECIAL-FUNCTION REGISTER (SECTION I)
INDEX OF SPECIAL-FUNCTION REGISTER (SECTION II)
—
—
—
—
—
CRNG
00010
EIE0
—
—
—
—
—
—
—
—
—
—
CRSLT2L
01010
—
—
—
—
—
—
—
—
—
—
—
00011
EIES0
PD
and the processor is initiated through the interrupt han-
dler. SFRs can be 8-bit or 16-bit registers and most of the
SFRs are accessible by user software (Tables 6, 7, 8). All
undefined or unallocated registers should be treated as
reserved registers.
—
—
—
—
LOCK ICDT0 ICDT1 ICDC ICDF ICDB
DESCRIPTION
—
—
—
—
—
CRSLT2H
01011
—
—
—
—
—
—
—
—
—
—
00100
TCON
WU1
—
—
—
—
01100
AT1H
—
—
—
—
—
TM2
—
—
—
—
—
—
—
—
—
00101
TFRQ
WU2
—
—
—
—
01101
RT1H
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
00110
TCNT
FEL
—
—
—
—
01110
AT2H
—
—
—
—
—
ICDA
—
—
—
—
—
ICDD
—
—
—
—
—
00111
01111
BRKP
FEB
RT2H
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—