LAN8700C-AEZG-TR SMSC, LAN8700C-AEZG-TR Datasheet - Page 79

• Manufacturer Part Number: LAN8700C-AEZG-TR
• Description: Ethernet ICs Hi Perform Ethernet PHY
• Manufacturer: SMSC
• Type: Single Chipr

Specifications of LAN8700C-AEZG-TR

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: IEEE 802.3ab
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Supply Current (max): 39 mA, 81.6 mA
• Maximum Operating Temperature: + 85 C
• Package / Case: QFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR
Datasheet
SMSC LAN8700/LAN8700i
REVISION LEVEL
(02-14-08)
(02-14-08)
(10-04-07)
(09-17-07)
(06-27-07)
(06-27-07)
(05-29-07)
(05-29-07)
(05-23-07)
(05-23-07)
(05-23-07)
(05-23-07)
(05-23-07)
(05-23-07)
(04-17-07)
(04-17-07)
(12-11-07)
(12-11-07)
(12-11-07)
(12-11-07)
& DATE
Rev. 1.8
Rev. 1.8
Rev. 1.6
Rev. 1.6
Rev. 1.6
Rev. 1.6
Rev. 1.5
Rev. 1.4
Rev. 1.3
Rev. 1.3
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.1
Rev. 1.1
Table 6.7
Table 6.6
Section 4.9
Table 3.8, "Power Signals"
Table 3.1, "MII Signals"
Table 5.33, "Register 3 - PHY
Identifier 2"
Chapter 8, Application Notes
Section 7.1.4
Table 6.9
Table 6.5
Table 5.48
Table 5.30
Section 5.4.9.2
Table 5.30
Table 3.5
Table 7.11
Table 3.1
Table 6.7
Table 7.4
Table 3.4
SECTION/FIGURE/ENTRY
Table 10.1 Customer Revision History (continued)
DATASHEET
®
79
Technology in a Small Footprint
Changed value of T8.1 and T8.2
Changed value of T6.1
Added information about not applying VDD_CORE
before VDD33 is at 2.64V.
Updated description of VDD_CORE for information
on using external 1.8V supply.
Updated description of RX_CLK/REGOFF to add
power supply sequencing information.
Updated Revision Number to match the LAN8700C
silicon.
Figure 8.1
following cross reference added to caption:
(see
Changed VIH to 0.68*VDDIO.
Changed VIL to 0.4*VDDIO.
Moved parameter T10.2 in
column to MIN column.
Moved parameter T5.2 in
column to MIN column.
Added description when the MODE[2:0] bits are set
to 110.
Corrected Default value for bit 0.11 to the value of
0. This bit does not get set when the MODE[2:0]
bits are set to 110.
Added detail about MODE[2:0] pins having no
affect at soft reset.
Added note to reset description (bit 0.15).
AT nRST, added note that register bit values are
loaded from the Mode pins upon deassertion.
Added RX_DV to table.
Added note that RX_DV and RX_ER cannot be
high during reset.
Moved parameter T8.2 from MAX column to MIN
column.
Changed column headings to add clarity regarding
source of current. Added Note.
Removed RX_CLK/REGOFF because it made
Note 3.1
Section 8.4, "Reference
false.
has been updated. In addition, the
CORRECTION
Table 6.5
Table 6.9
Designs")
Revision 2.2 (12-04-09)
from MAX
from MAX