WM8731LSEFL/R Wolfson Microelectronics, WM8731LSEFL/R Datasheet - Page 44

• Manufacturer Part Number: WM8731LSEFL/R
• Description: Audio CODECs STEREO CODEC w/ HP 28-pin
• Manufacturer: Wolfson Microelectronics

Specifications of WM8731LSEFL/R

• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Conversion Rate: 96 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, I2S)
• Resolution: 18 bit, 20 bit
• Operating Supply Voltage: - 0.3 V to + 3.63 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN EP
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 2 ADC/2 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8731 / WM8731L
w
((Note 1)
USB MODE SAMPLE RATES
In USB mode the MCLK/crystal oscillator input is 12MHz only.
Notes:
1.
2.
3.
4.
The table above can be used to set up the device to work with various sample rate combinations. For
example if the user wishes to use the WM8731/L in USB mode with the ADC and DAC sample rates
at 48kHz and 48kHz respectively then the device should be programmed with BOSR = 0, SR3 = 0,
SR2 = 0, SR1 = 0 and SR0 = 0. The ADC and DAC will then operate with a Digital Filter of type 0,
refer to Digital Filter Characteristics section for an explanation of the different filter types.
The BOSR bit represents the base over-sampling rate. This is the rate that the WM8731/L digital
signal processing is carried out at and the sampling rate will always be a sub-multiple of this. In USB
mode, with BOSR = 0, the base over-sampling rate is defined at 250fs, with BOSR = 1, the base
over-sampling rate is defined at 272fs. This can be used to determine the actual audio sampling rate
produced by the ADC and required by the DAC.
Example scenarios are, :-
1.
2.
Table 21 USB Mode Sample Rate Look-up Table
(Note 2)
(Note 1)
(Note 3)
(Note 2)
ADC
44.1
44.1
88.2
kHz
48
48
32
96
SAMPLING
8
8
8
8
8k not exact, actual = 8.021kHz
44.1k not exact, actual = 44.118kHz
88.2k not exact, actual = 88.235kHz
All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid
with a requirement that the ADC data sampling rate is 8kHz and DAC data sampling rate is
48kHz the device is programmed with BOSR = 0 (250fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 =
0.The ADC will then be exactly 8kHz ( derived from 12MHz/250 x 1/6 ) and the DAC expects
data at exactly 48kHz ( derived from 12MHz/250 ).
with a requirement that ADC data rate is 8kHz and DAC data rate is 44.1kHz the device is
programmed with BOSR = 1 (272fs), SR3 = 1, SR2 = 0, SR1 = 1, SR0 = 0. The ADC will not
output data at exactly 8kHz, instead it will be 8.021kHz ( derived from 12MHz/272 x 2/11 ) and
the DAC at 44.118kHz ( derived from 12MHz/272 ). A slight (sub 0.5%) pitch shift will therefore
results in the 8kHz and 44.1kHz audio data and (more importantly) the user must ensure that
the data across the digital interface is correctly synchronised at the 8.021kHz and 44.117kHz
rates.
RATE
(Note 2)
(Note 1)
(Note 2)
(Note 1)
(Note 3)
DAC
44.1
44.1
88.2
kHz
48
48
32
96
8
8
8
8
FREQUENCY
12.000
12.000
12.000
12.000
12.000
12.000
12.000
12.000
12.000
12.000
12.000
MCLK
MHz
BOSR
0
1
0
1
0
1
0
1
0
0
1
SR3
REGISTER SETTINGS
0
1
0
1
0
1
0
1
0
0
1
SAMPLE
RATE
SR2
0
0
0
0
0
0
0
0
1
1
1
SR1
0
0
0
0
1
1
1
1
1
1
1
PD, Rev 4.8, April 2009
SR0
0
0
1
1
0
0
1
1
0
1
1
Production Data
DIGITAL
FILTER
TYPE
0
1
0
1
0
1
0
1
0
3
2
44