LC4256ZE-P-EVN Lattice, LC4256ZE-P-EVN Datasheet - Page 11

• Manufacturer Part Number: LC4256ZE-P-EVN
• Description: Development Software ispMACH 4000ZE Pico Eval Board
• Manufacturer: Lattice
• Series: ispMACH®r
• Type: CPLDr

Specifications of LC4256ZE-P-EVN

• Tool Type: Development Software Kit
• Core Architecture: CPLD
• Silicon Manufacturer: Lattice Semiconductor
• Kit Contents: Evaluation Board, USB Connector Cable. Quick Start Guide
• Features: High-Side Current Sensor Circuits
• Svhc: No SVHC (15-Dec-2010)
• Rohs Compliant: Yes
• Contents: Board, Cable, Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: LC4256ZE-5MN144C

Lattice Semiconductor
Figure 9. Power Guard
All the I/O pins in a block share a common Power Guard Enable signal. For a block of I/Os, this signal is called a
Block Input Enable (BIE) signal. BIE can be internally generated using MC logic, or could come from external
sources using one of the user I/O or input pins.
Any I/O pin in the block can be programmed to ignore the BIE signal. Thus, the feature can be enabled or disabled
on a pin-by-pin basis.
Figure 10 shows Power Guard and BIE across multiple I/Os in a block that has eight I/Os.
Figure 10. Power Guard and BIE in a Block with 8 I/Os
Block Input Enable (BIE)
From Block PT. The Block PT
is part of the block AND Array,
and can be driven by signals
from the GRP.
D
Power Guard
To Macrocell
To GRP
To Macrocell
To GRP
To Macrocell
To GRP
E
0
1
11
Q
ispMACH 4000ZE Family Data Sheet
Power Guard
Power Guard
Power Guard
0
1
0
1
0
1
I/O 0
I/O 1
I/O 7