ACPL-H342-060E Avago Technologies US Inc., ACPL-H342-060E Datasheet - Page 17
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ACPL-H342-060E
Manufacturer Part Number
ACPL-H342-060E
Description
Logic Output Optocouplers Optocoupler
Manufacturer
Avago Technologies US Inc.
Series
-r
Type
Gate Driver, Miller Clampr
Datasheet
1.ACPL-K342-000E.pdf
(19 pages)
Specifications of ACPL-H342-060E
Fall Time
18 ns
Rise Time
22 ns
Maximum Propagation Delay Time
0.35 us
Maximum Forward Diode Voltage
1.95 V
Minimum Forward Diode Voltage
1.2 V
Maximum Reverse Diode Voltage
5 V
Maximum Continuous Output Current
2.5 A
Maximum Power Dissipation
255 mW
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Package / Case
SOIC-8
No. Of Channels
1
Isolation Voltage
3.75kV
Optocoupler Output Type
Gate Drive
Input Current
230mA
Output Voltage
30V
Opto Case Style
SOIC
No. Of Pins
8
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Voltage - Isolation
3750Vrms
Input Type
DC
Voltage - Supply
15 V ~ 30 V
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Leaded Process Compatible
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Anti-Cross Conduction to Prevent Current Shoot Through and Determining Dead Time
The ACPL-H342 includes a Propagation Delay Difference (PDD = t
high(Q1) and low(Q2) side power transistors from turning on at the same time. This “Anti-Cross” conduction feature
prevents large currents from flowing through the power transistors by ensuring t
words, the “Anti-Cross” feature will ensure one power transistor is turned off before the other is turned on.
A gate driver without Anti-Cross feature will for example has a PDD
PDD
This is shown in Figure 37. To prevent this and the shoot through current, the turn on of LED2 should be delayed (relative
to the turn off of LED1) so that under worst-case conditions, Q1 has just turned off when Q2 turns on. The amount of
delay to achieve this condition is equal to PDD
Figure 37. Current shoot through without Anti-Cross feature
17
I
V
V
I
LED1
LED2
OUT1
OUT2
MAX
Q2 OFF
of 350ns would mean one transistor will be turn on before the other is off since t
t
PLHMIN
t
PHLMAX
High Side PWM
Low Side PWM
Through
Shoot
Q1 ON
Q2 ON
Q1 OFF
R
R
MAX
LED1
LED2
as shown in Figure 38.
Figure 38. Adding delay to prevent shoot through
I
V
V
I
LED1
LED2
OUT1
OUT2
V
V
OUT1
OUT2
PHL
R
R
MIN
G
G
– t
of -350ns and a PDD
PLH
Q1
Q2
PDD
) specification to help prevent both the
PHLMAX
MAX
= t
Q1 ON
t
Q2 OFF
PHLMAX
PHLMAX
is faster than t
t
+ HVDC
AC
-HVDC
PHLMAX
PLHMIN
- t
PLHMIN
MAX
is longer than t
= 350 ns
Q1 OFF
Q2 ON
of 350ns. A positive
PLHMIN
. In another
PLHMIN
.