TSL201R-LF TAOS, TSL201R-LF Datasheet - Page 2

• Manufacturer Part Number: TSL201R-LF
• Description: Photodiodes Linear Sensor Array 200dpi 64pix
• Manufacturer: TAOS
• Type: Linear Sensor Arrayr

Specifications of TSL201R-LF

• Peak Wavelength: 1000 nm
• Maximum Rise Time: 500 ns
• Maximum Fall Time: 500 ns
• Package / Case: PDIP-8
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Product: Photodiode
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TSL201R−LF
64 y 1 LINEAR SENSOR ARRAY
TAOS077B − MAY 2007
Terminal Functions
Detailed Description
2
Copyright E 2007, TAOS Inc.
†
The sensor consists of 64 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During
the integration period, a sampling capacitor connects to the output of the integrator through an analog switch.
The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration
time. The integration time is the interval between two consecutive output periods.
The output and reset of the integrators is controlled by a 64-bit shift register and reset logic. An output cycle is
initiated by clocking in a logic 1 on SI for one positive going clock edge (see Figures1 and 2)
is clocked through the 64-bit shift register, the charge on the sampling capacitor of each pixel is sequentially
connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes
low, the pixel integrator is reset. On the 65
and the output assumes a high-impedance state. Note that this 65
output of the 64
as early as the 66
The voltage developed at analog output (AO) is given by:
where:
AO is driven by a source follower that requires an external pulldown resistor (330-Ω typical). The output is
nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device
is not in the output phase, AO is in a high impedance state.
A 0.1 μF bypass capacitor should be connected between V
For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock.
V
V
R
E
t
int
out
drk
e
e
is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(μJ/cm
is the incident irradiance in μW/cm
is integration time in seconds
NAME
AO
CLK
GND
SI
V
th
TERMINAL
DD
pixel and return the internal logic to a known state. A subsequent SI pulse can be presented
th
clock pulse, thereby initiating another pixel output cycle.
NO.
6, 7
3
2
1
4
Analog output.
Clock. The clock controls charge transfer, pixel output, and reset.
Ground (substrate). All voltages are referenced to the substrate.
Serial input. SI defines the start of the data-out sequence.
Supply voltage. Supply voltage for both analog and digital circuits.
V
out
= V
r
drk
+ (R
www.taosinc.com
th
e
clock rising edge, the SI pulse is clocked out of the shift register
2
) (E
e
) (t
int
DESCRIPTION
DESCRIPTION
)
DD
and ground as close as possible to the device.
th
clock pulse is required to terminate the
r
2
The LUMENOLOGY r Company
)
†
. As the SI pulse