TSL2014 TAOS, TSL2014 Datasheet - Page 2

• Manufacturer Part Number: TSL2014
• Description: Photodiodes Linear Array 200 DPI
• Manufacturer: TAOS
• Type: Linear Sensor Arrayr

Specifications of TSL2014

• Peak Wavelength: 1000 nm
• Maximum Rise Time: 500 ns
• Maximum Fall Time: 500 ns
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Product: Photodiode
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TSL2014
896 y 1 LINEAR SENSOR ARRAY
TAOS040B − MAY 2007
Terminal Functions
Detailed Description
2
Copyright E 2007, TAOS Inc.
AO1
AO2
CLK
GND
SI1
SI2
SO1
SO2
VDD
NAME
TERMINAL
†
The sensor consists of 896 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During
the integration period, a sampling capacitor connects to the output of the integrator through an analog switch.
The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration
time. The integration time is the interval between two consecutive output periods.
The output and reset of the integrators is controlled by two 448-bit shift registers and reset logic. A 448-pixel
output cycle is initiated by clocking in a logic 1 into the SI input of a section for one positive going clock edge
(see Figures1 and 2)
or connected in series to form a 896-pixel array. Each section has an independent output (AO), which may be
connected together for the 896-pixel function.
When operating in the 896-pixel mode, as the SI pulse is clocked through the 896-bit shift register, the charge
on the sampling capacitor of each pixel is sequentially connected to a charge-coupled output amplifier that
generates a voltage output, AO. When the bit position goes low, the pixel integrator is reset. On the 897
rising edge, the SI pulse is clocked out of the shift register (S2) and the output assumes a high-impedance state.
Note that this 897
to a known state. A subsequent SI pulse can be presented as early as the 898
another pixel output cycle.
The voltage developed at analog output (AO) is given by:
where:
AO is driven by a source follower that requires an external pulldown resistor (330-Ω typical). The output is
nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device
is not in the output phase, AO is in a high impedance state.
A 0.1 μF bypass capacitor should be connected between V
For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock.
1, 10
V
V
R
E
t
NO.
int
out
drk
e
e
3
8
6
7
2
5
4
9
I/O
I/O
O
O
O
O
is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(μJ/cm
is the incident irradiance in μW/cm
is integration time in seconds
I
I
I
th
Analog output of section 1.
Analog output of section 2.
Clock. The clock controls the charge transfer, pixel output and reset.
Ground (substrate). All voltages are referenced to GND.
Serial input (section 1). SI1 defines the start of the data-out sequence.
Serial input (section 2). SI2 defines the start of the data-out sequence.
Serial output (section 1). SO1 signals the end of the data out sequence and provides a signal to drive the input
of section 2 (SI2) in serial mode.
Serial output (section 2). SO2 signals the end of the data out sequence and provides a signal to drive the input
of another device for cascading.
Supply voltage. Supply voltage for both analog and digital circuits.
clock pulse is required to terminate the output of the 896
†
. The two 448-pixel sections may be operated independently using a single clock input
V
out
= V
r
drk
+ (R
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2
) (E
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int
)
DESCRIPTION
DESCRIPTION
DD
and ground as close as possible to the device.
r
th
pixel and return the internal logic
th
clock pulse, thereby initiating
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th
clock