LM2512SM/NOPB National Semiconductor, LM2512SM/NOPB Datasheet - Page 6

• Manufacturer Part Number: LM2512SM/NOPB
• Description: IC SERIALIZER 24BIT RGB 49-UFBGA
• Manufacturer: National Semiconductor
• Series: LMr

Specifications of LM2512SM/NOPB

• Function: Serializer
• Data Rate: 468Mbps
• Input Type: LVCMOS
• Output Type: LVCMOS
• Number Of Inputs: 21
• Number Of Outputs: 3
• Voltage - Supply: 1.6 V ~ 3 V
• Operating Temperature: -30°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 49-UFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM2512SM

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PIXEL CLOCK (PCLK)
f
PCLK
t
t
SPI INTERFACE
f
f
t
t
t
t
t
t
t
t
t
t
PCLK
T
STOPpclk
SCLw
SCLr
s0
s1
h1
w1h
w1l
r
f
0H
h0
w2
Symbol
Recommended Input Timing Requirements (PCLK and SPI)
Over recommended operating supply and temperature ranges unless otherwise specified.
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
Note 3: Current into a device pin is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to Ground unless otherwise
specified.
Note 4: For IDD tests - input signal conditions are: (swing, edge, freq, DE = H, VS = L, HS = L, RGB Checkerboard Pattern: AAAAAA-555555)
Note 5: Total Supply Current Conditions: checkerboard data pattern, 20MHz PCLK (3MDs), TYP V
= VDD = 2.0V.
Note 6: Enable Time is a complete MPL start up comprised of t0 + t1 + t2 + t3 + t4.
Note 7: Maximum transition time is a function of clock rate and should be less than 30% of the clock period to preserve signal quality.
Note 8: Guaranteed functionally by the I
Note 9: This is the minimum time that the PCLK needs to be held off for in order for the device to be reset. Once PCLK is reapplied, a PLL Lock is required and
start up sequence before video data is serialized.
Note 10: 1 UI is the serial data MD pulse width = 1 / 8xPCLK (3 MD lanes)
Note 11: This is a functional parameter and is guaranteed by design or characterization.
Note 12: Upon power-up, the LUT SRAMs may not be in their lowest power state. To ensure that the SRAMs have entered their lowest power state, a single SPI
access to each of the three SRAMs is recommended. The IDDz current specification assumes that each of the three SRAMs has been accessed at least once.
For additional information, please refer to the "Power Up Sequence" section in the datasheet.
DC
Pixel Clock Frequency
Pixel Clock Duty Cycle
Transition Time
Clock Stop Gap
SCL Frequency
CSX Set Time
SI Set Time
SI Hold Time
SCL Pulse Width High
SCL Pulse Width Low
SCL Rise Time
SCL Fall Time
SI Hold Time
CSX Hold Time
CSX OFF Time
Parameter
DDIO
DDZ
= 1.8V and V
201728 Version 5 Revision 1
parameter. See also
3 MD Lane, (4X)
2 MD Lane, (6X)
(Note
(Note
WRITE
READ
Figure 15
Figures 15, 16
Figure 15
DD
7,
9,
= V
Note
Note
DDA
Figure
= 1.8V and T
11)
11)
Conditions
10.
WRITE
READ
WRITE
READ
Print Date/Time: 2010/01/20 21:11:52
6
A
= 25°C.
DDIO
= V
DDA
Min
100
7.5
30
60
30
30
35
60
35
60
30
65
5
2
4
= V
(Note
DD
= 1.8V, MAX VDDIO = 3.0V, MAX VDDA
2)
Typ
50
>2
2
5
5
Max
22.5
6.67
15
70
10
cycles
PCLK
Units
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%