WJLXT971ALE.A4-857343 Cortina Systems Inc, WJLXT971ALE.A4-857343 Datasheet - Page 37

• Manufacturer Part Number: WJLXT971ALE.A4-857343
• Description: TXRX ETH 10/100 SGL PORT 64-LQFP
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT971ALE.A4-857343

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1041

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
5.6.1
Note:
Cortina Systems
The LXT971A PHY implements the Media Independent Interface (MII) as defined by the
IEEE 802.3 standard. Separate channels are provided for transmitting data from the MAC
to the LXT971A PHY (TXD), and for passing data received from the line (RXD) to the
MAC. Each channel has its own clock, data bus, and control signals.
The following signals are used to pass received data to the MAC:
The following signals are used to transmit data from the MAC:
The LXT971A PHY supplies both clock signals as well as separate outputs for carrier
sense and collision. Data transmission across the MII is normally implemented in 4-bit-
wide nibbles.
MII Clocks
The LXT971A PHY is the master clock source for data transmission, and it supplies both
MII clocks (RX_CLK and TX_CLK). It automatically sets the clock speeds to match link
conditions.
Figure 10
The transmit data and control signals must always be synchronized to TX_CLK by the
MAC. The LXT971A PHY samples these signals on the rising edge of TX_CLK.
®
• COL
• CRS
• RX_CLK
• RX_DV
• RX_ER
• RXD[3:0]
• TX_CLK
• TX_EN
• TX_ER
• TXD[3:0]
• When the link is operating at 100 Mbps, the clocks are set to 25 MHz.
• When the link is operating at 10 Mbps, the clocks are set to 2.5 MHz.
LXT971A Single-Port 10/100 Mbps PHY Transceiver
through
Figure 12
show the clock cycles for each mode.
5.6 MII Operation
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