WJLXT972ALC.A4-857345 Cortina Systems Inc, WJLXT972ALC.A4-857345 Datasheet - Page 6

• Manufacturer Part Number: WJLXT972ALC.A4-857345
• Description: TXRX ETH 10/100 SGL PORT 64-LQFP
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT972ALC.A4-857345

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1043-2

LXT972A PHY
Datasheet
249186, Revision 5.2
13 September 2007
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Cortina Systems
Related Documents ....................................................................................................................... 10
PHY Signal Types ......................................................................................................................... 12
LQFP Numeric Pin List .................................................................................................................. 13
PHY Signal Types ......................................................................................................................... 15
MII Data Interface Signal Descriptions .......................................................................................... 16
MII Controller Interface Signal Descriptions .................................................................................. 17
LXT972A: Network Interface Signal Descriptions.......................................................................... 17
LXT972A: Standard Bus and Interface Signal Descriptions .......................................................... 17
LXT972A: Configuration and LED Driver Signal Descriptions ....................................................... 18
LXT972A: Power, Ground, No-Connect Signal Descriptions ........................................................ 19
LXT972A: JTAG Test Signal Descriptions..................................................................................... 19
LXT972A: Pin Types and Modes................................................................................................... 20
Hardware Configuration Settings................................................................................................... 28
Carrier Sense, Loopback, and Collision Conditions ...................................................................... 33
4B/5B Coding ................................................................................................................................ 39
BSR Mode of Operation ................................................................................................................ 46
Device ID Register......................................................................................................................... 46
Magnetics Requirements............................................................................................................... 47
I/O Pin Comparison of NIC and Switch RJ-45 Setups................................................................... 47
Absolute Maximum Ratings ...........................................................................................................51
Recommended Operating Conditions ........................................................................................... 51
Digital I/O Characteristics (Except for MII, XI/XO, and LED/CFG Pins) ........................................ 52
Digital I/O Characteristics
I/O Characteristics - REFCLK/XI and XO Pins .............................................................................. 53
I/O Characteristics - LED/CFG Pins ..............................................................................................53
100BASE-TX PHY Characteristics ................................................................................................ 53
10BASE-T PHY Characteristics .................................................................................................... 54
10BASE-T Link Integrity Timing Characteristics............................................................................ 54
Thermal Characteristics................................................................................................................. 54
100BASE-TX Receive Timing Parameters - 4B Mode .................................................................. 56
10BASE-T Receive Timing Parameters ........................................................................................ 57
10BASE-T Jabber and Unjabber Timing ....................................................................................... 58
PHY 10BASE-T SQE (Heartbeat) Timing...................................................................................... 58
Auto-Negotiation and Fast Link Pulse Timing Parameters ............................................................ 59
MDIO Timing ................................................................................................................................. 60
Power-Up Timing ........................................................................................................................... 61
RESET_L Pulse Width and Recovery Timing ............................................................................... 62
Register Set for IEEE Base Registers ........................................................................................... 63
Control Register - Address 0, Hex 0 ..............................................................................................64
MII Status Register #1 - Address 1, Hex 1 .................................................................................... 65
PHY Identification Register 1 - Address 2, Hex 2 .......................................................................... 66
PHY Identification Register 2 - Address 3, Hex 3 .......................................................................... 66
Auto-Negotiation Advertisement Register - Address 4, Hex 4....................................................... 67
Auto-Negotiation Link Partner Base Page Ability Register - Address 5, Hex 5 ............................. 68
Auto-Negotiation Expansion - Address 6, Hex 6 ........................................................................... 69
Auto-Negotiation Next Page Transmit Register - Address 7, Hex 7 .............................................. 69
Auto-Negotiation Link Partner Next Page Receive Register - Address 8, Hex 8 .......................... 70
Register Set for Product-Specific Registers ..................................................................................71
®
LXT972A Single-Port 10/100 Mbps PHY Transceiver
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- MII Pins ............................................................................................ 52
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