LAN7500I-ABZJ SMSC, LAN7500I-ABZJ Datasheet - Page 7

• Manufacturer Part Number: LAN7500I-ABZJ
• Description: IC USB-10/100/1K ETH CTRL 56QFN
• Manufacturer: SMSC

Specifications of LAN7500I-ABZJ

• Design Resources: LAN7500I BOM LAN7500I Schematic
• Controller Type: Ethernet Controller, USB 2.0 to 10/100/1K
• Interface: USB/Serial
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 638-1109

Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller
Datasheet
Chapter 1 Introduction
SMSC LAN7500/LAN7500i
1.1
1.1.1
JTAG
USB
LAN7500/LAN7500i
Block Diagram
Controller
USB
PHY
Overview
The LAN7500/LAN7500i is a high performance Hi-Speed USB 2.0 to 10/100/1000 Ethernet controller.
With applications ranging from embedded systems, set-top boxes, and PVR’s, to USB port replicators,
USB to Ethernet dongles, and test instrumentation, the device is a high performance and cost
competitive USB to Ethernet connectivity solution.
The LAN7500/LAN7500i contains an integrated 10/100/1000 Ethernet MAC and PHY, Filtering Engine,
USB PHY, Hi-Speed USB 2.0 device controller, TAP controller, EEPROM controller, and a FIFO
controller with a total of 32 KB of internal packet buffering.
The internal USB 2.0 device controller and USB PHY are compliant with the USB 2.0 Hi-Speed
standard. The device implements Control, Interrupt, Bulk-in, and Bulk-out USB Endpoints.
The Ethernet controller supports auto-negotiation, auto-polarity correction, HP Auto-MDIX, and is
compliant with the IEEE 802.3, IEEE 802.3u, IEEE 802.3ab standards. ARP and NS offload is also
supported.
Multiple power management features are provided, including various low power modes and "Magic
Packet", "Wake On LAN", and "Link Status Change" wake events. These wake events can be
programmed to initiate a USB remote wakeup.
An internal EEPROM controller exists to load various USB configuration information and the device
MAC address. The integrated IEEE 1149.1 compliant TAP controller provides boundary scan via JTAG.
TAP
Controller
USB 2.0
Device
Figure 1.1 LAN7500/LAN7500i System Diagram
Controller
SRAM
FIFO
DATASHEET
7
Filtering
Receive
Engine
Ethernet
10/100/
1000
MAC
Controller
EEPROM
Ethernet
Revision 1.0 (11-01-10)
PHY
Ethernet
EEPROM