73S8024C-ILR/F Maxim Integrated Products, 73S8024C-ILR/F Datasheet - Page 10

• Manufacturer Part Number: 73S8024C-ILR/F
• Description: IC SMART CARD INTERFACE 28-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of 73S8024C-ILR/F

• Controller Type: Smart Card Interface
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Interface: -

73S8024C Data Sheet
The following steps and
when the system controller pulls CMDVCC low while RSTIN is high:
1. CMDVCC is set low.
2. Next, the internal V
3. After the fall of RSTIN at t
4. CLK is applied to the card at the end of t
5. RST is a copy of RSTIN after t
9 Deactivation Sequence
Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in
the event of hardware faults. Hardware faults are over-current, overheating, V
extraction during the session.
The following steps and
when the system controller sets the CMDVCC high or OFF goes low due to a fault or card removal:
1. RST goes low at the end of time t
2. CLK is set low at the end of time t
3. I/O goes low at the end of time t
4. V
10
the voltage V
the system controller and the V
set RST high until 42,000 clock cycles after the start of CLK.
CMDVCC
CC
RSTIN
t
t
t
1
2
4
is turned off at the end of time t
VCC
CLK
RST
= 0.510 ms (timing by 1.5MHz internal Oscillator)
= 1.5 µs, I/O goes to reception state
≥ 42000 card clock cycles (time for RST to become the copy of RSTIN).
IO
Figure 4: Activation Sequence – RSTIN high when CMDVCC goes low
CC
to the card becomes valid during this time. If not, OFF goes low to report a fault to
CC
Figure 5
Figure 4
control circuit checks the presence of V
2
, turn I/O (AUX1, AUX2) to reception mode.
t
show the deactivation sequence and the timing of the card control signals
1
show the activation sequence and the timing of the card control signals
4
CC
. RSTIN may be set high before t
3
. Out of reception mode.
1
2
power to the card is shut down.
.
.
4
. After a delay t
3
t
3
after I/O is in reception mode.
≥ 0.5 µs, CLK active
t
2
5
(discharge of the V
t
3
CC
at the end of t
4
, however the sequencer will not
t
4
CC
DD
capacitor), V
fault, V
1
. In normal operation,
CC
DS_8024C_023
fault, and card
CC
is low.
Rev. 1.3