RPCS3472C.A1-998970 Cortina Systems Inc, RPCS3472C.A1-998970 Datasheet - Page 2

• Manufacturer Part Number: RPCS3472C.A1-998970
• Description: IC ETH MAC 24-PORT 1152-UPBGA
• Manufacturer: Cortina Systems Inc

Specifications of RPCS3472C.A1-998970

• Controller Type: Ethernet Controller, MAC
• Interface: Interlaken, XAUI
• Voltage - Supply: *
• Current - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1026

Copyright © 2007 - 2008 Cortina Systems, Inc.
Summary of Features and Benefits
Functionality:
• 24x 10/100/1000 Mbps Ethernet MACs
• A high-speed channelized Interlaken
• Rule-based layer 5 classification engine with
• 24 port line r ate operation
• Oversubscribed operation with four queues
• Internal memory or external memory
• Random Early Discard (RED) support
• Priority marking of DSCP and 802.1p fields
• Committed and burstable r ates enforced
• MEF per-VLAN policing, statistics, and tagging
• Assign lower priority to ex cess frames
• Jumbo frame support
• Ethernet MIB and RMON
• Supports synchronous Ethernet timing
Interfaces:
• 24x SGMII to 10/100/1000 Mbps Ethernet
• 24x serial GE and FE (100BA SE-FX) to optical
• Number of lanes and bitr ates for uplink is
• 250 MHz QDR-II/II+ SRAM interface for
• Generic parallel microprocessor bus
• LED status port
• MDIO master port to control tri-speed copper
• JTAG and GPIO ports
Technology:
• 1152 ball, 35x35mm organic Ultr a-Performance
uplink
IPv6 support
per ports
oversubscription
distribution
Copper PHYs
SFP modules
scalable
- 5-lane Interlaken uplink at 6.25 Gbps bit
- 8-lane Interlaken uplink at 4.25 Gbps
optional oversubscription buffering
PHYs
Ball Grid Array (UPBGA) package
rate; or
bit rate
• Partners with Cortina S ystems
• Supports new Metro synchronization
• Combines all SerDes, PHY, and MAC classification
• Offers a very high-density line-rate or over-
• Delivers extensive QoS for ov ersubscribed line
• Integrates a rule-based la yer 5 classification
• Connects to the host through the Interlak en
• Integrates a JTAG interface that is IEEE 1149.1
• Supports store-and-forward mode and a low-
• Reduces board complexity through native
• Integrates Clock and Data R ecovery (CDR)
• Contains ECC protected internal memories
create a complete GE & 10 GE Interlak en
solution
requirements
and policing functions into a single device
reducing complexity and cost
subscription aggregation front -end solution
cards through a combination of a deep
packet classifier, 4 queues per ingress port,
deep external oversubscription memories, and
multiple scheduling modes
and IPv6 support to meet QoS requirements
interface (a high-speed, channeliz ed packet
interface) or through two XA UI interfaces
compliant
latency cut-through mode independently in RX
and TX directions
connections to optical SFP modules and
copper SGMII PHYs
removing the need for external clocking
®
Product Brief Number: 400016-1.1
CS3477 to