73S8024RN-IL/F Maxim Integrated Products, 73S8024RN-IL/F Datasheet - Page 13

• Manufacturer Part Number: 73S8024RN-IL/F
• Description: IC SMART CARD INTERFACE 28-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Low Cost Smart Card Interfacer

Specifications of 73S8024RN-IL/F

• Controller Type: Smart Card Interface
• Voltage - Supply: 2.7 V ~ 5.5 V
• Current - Supply: 2.7mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS_8024RN_020
9 OFF and Fault Detection
There are two different cases that the system controller can monitor the OFF signal: to query regarding
the card presence outside card sessions, or for fault detection during card sessions.
Outside a card session: In this condition, CMDVCC is always high, OFF is low if the card is not present,
and high if the card is present. Because it is outside a card session, any fault detection will not act upon
the OFF signal. No deactivation is required during this time.
During a card session: CMDVCC is always low, and OFF falls low if the card is extracted or if any fault
detection is detected. At the same time that OFF is set low, the sequencer starts the deactivation
process.
The Figure 5 shows the timing diagram for the signals CMDVCC, PRES, and OFF during a card session
and outside the card session:
10 I/O Circuitry and Timing
The states of the I/O, AUX1, and AUX2 pins are low after power on reset and they are in high when the
activation sequencer turns on the I/O reception state. See the
details on when the I/O reception is enabled. The states of I/OUC, AUX1UC, and AUX2UC are high after
power on reset.
Within a card session and when the I/O reception state is turn on, the first I/O line on which a falling edge
is detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line
rising edge is detected then both I/O lines return to their neutral state.
Figure 6
The delay between the I/O signals is shown in Figure 7.
Rev. 1.9
CMDVCC
shows the state diagram of how the I/O and I/OUC lines are managed to become input or output.
VCC
PRES
OFF
Figure 5: Timing Diagram – Management of the Interrupt Line OFF
outside card session
within card session
Activation Sequence
card extracted
OFF is low by
73S8024RN Data Sheet
section for more
within card
session
OFF is low by
any fault
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