PK40X256VMD100 Freescale Semiconductor, PK40X256VMD100 Datasheet - Page 39

• Manufacturer Part Number: PK40X256VMD100
• Description: IC ARM CORTEX MCU 256K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK40X256VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
• Peripherals: DMA, I²S, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 33x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Rohs Compliant: YES
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 64 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 98
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

1. Typical values assume V
2. ADC must be configured to use the internal voltage reference (VREF_OUT)
3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
4. For single ended configurations the input impedance of the driven input is R
5. The analog source resistance (R
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
6.6.1.4 16-bit ADC with PGA characteristics
Freescale Semiconductor, Inc.
I
Symbol
Symbol
DDA_PGA
R
V
reference only and are not tested in production.
than the output of the VREF module, the VREF module must be disabled.
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
time should be allowed for F
8 MHz ADC clock.
C
V
R
PGAD
ADIN
T
rate
CM
AS
S
Input voltage
Input Common
Mode range
Differential input
impedance
Analog source
resistance
ADC sampling
time
ADC conversion
rate
Description
Supply current
Description
Table 27. 16-bit ADC with PGA operating conditions (continued)
DDA
Table 28. 16-bit ADC with PGA characteristics
K40 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
in
Gain = 1, 2, 4, 8
Gain = 16, 32
Gain = 64
≤ 13 bit modes
No ADC hardware
averaging
Continuous
conversions enabled
Peripheral clock = 50
MHz
16 bit modes
No ADC hardware
averaging
Continuous
conversions enabled
Peripheral clock = 50
MHz
Conditions
= 3.0 V, Temp = 25°C, f
=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
Low power
(ADC_PGA[PGALPb]=0)
Conditions
AS
), external to MCU, should be kept as minimum as possible. Increased R
Table continues on the next page...
Preliminary
ADCK
18.484
37.037
V
V
1.25
Min.
—
—
—
—
= 6 MHz unless otherwise stated. Typical values are for
SSA
SSA
Min.
—
Typ.
Peripheral operating requirements and behaviors
128
100
64
32
—
—
—
—
—
1
PGAD
Typ.
420
/2
1
V
V
Max.
450
250
—
—
—
—
—
DDA
DDA
Max.
TBD
Ksps
Ksps
Unit
kΩ
µs
V
V
Ω
Unit
μA
AS
IN+ to IN-
causes drop
Notes
Notes
5
6
7
8
2
4
39