EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 3

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2010-11-17 - d0021_Rev1.40
ID
EMU4
RTC1
USART1
WDOG2
Title/Problem
Sequencing of Analog and Digital
Power
Power-on Reset might fail if power is
applied to IOVDD_x or VDD_DREG
before AVDD_x
RTC PRS output
The RTC PRS output might cause
false triggers
U(S)ART Double Buffer
Transmission control through TX-
DATAX and TXDOUBLEX does not
work with data double buffering.
WDOG does not freeze in EM2/EM3
The WDOG keeps running in EM2
and EM3 even though EM2RUN and
EM3RUN bits in WDOG_CTRL are
programmed to 0.
Effect
The device might lock up if power is applied to IOVDD_x or
VDD_DREG pins before AVDD_x pins during power up. This
lock-up state can be exited by removing power to the device
followed by a power up sequence according to what is de-
scribed in the workaround.
If the RTC is selected as a PRS producer there might occur
glitches which will accidentally cause false triggers.
When a frame is loaded into the transmission shift register,
transmission control bits are always taken from outer buffer el-
ement. If only one frame is in the U(S)ART buffer, the content
of the buffer elements is equivalent, and transmission control
bits work as specified. If two frames are in the buffer howev-
er, the control bits for the frame in the outer buffer are used for
transmitting the frame in inner buffer. This is not a problem for
frames consisting of more than 9 bits, since these large frames
occupy both the inner and outer buffer elements.
If the WDOG is enabled when entering EM2 or EM3, a WDOG
reset will occur unless the system wakes up from EM2/EM3 (by
interrupt) and clears the WDOG timer before the WDOG times
out.
3
...the world's most energy friendly microcontrollers
Fix/Workaround
Make sure that the power on the AVDD_x pins ramp earlier or
at the same time as the power on IOVDD_x and VDD_DREG
during power up. Practical schematic recommendations for this
workaround are given in the EFM32 Application Note "AN0002
Hardware Design Considerations".
Do not use the RTC as a PRS producer, instead use one of the
other timer sources (e.g. TIMER0).
If using transmission control bits in registers TXDATAX or TX-
DOUBLEX make sure there are not more than one frame in
the U(S)ART buffer at a time, or that the control bits are equal.
When TXBL in U(S)ARTn_CTRL is cleared, the TXBL status
and interrupt flags in U(S)ARTn_STATUS and U(S)ARTn_IF
respectively tell when the buffer is empty. When using trans-
mission control bits, a single frame can then be loaded into the
USART for transmission.
Disable WDOG before entering EM2/EM3 by writing EN bit in
WDOG_CTRL to 0. This requires that the WDOG configuration
is unlocked (LOCK bit in WDOG_CTRL = 0). If WDOG config-
uration is locked, the WDOG will remain enabled in EM2/EM3
and the system must wake up the device from EM2/EM3 and
clear WDOG before WDOG times out.
www.energymicro.com