EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 62

MCU 32BIT 16KB FLASH 32-QFN

EFM32G200F16

Manufacturer Part Number
EFM32G200F16
Description
MCU 32BIT 16KB FLASH 32-QFN
Manufacturer
Energy Micro
Series
Geckor
Datasheets

Specifications of EFM32G200F16

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 4x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
EFM32G200
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
3.5.5 CMP and CMN
3.5.5.1 Syntax
3.5.5.2 Operation
3.5.5.3 Restrictions
3.5.5.4 Condition flags
3.5.5.5 Examples
3.5.6 MOV and MVN
3.5.6.1 Syntax
2011-02-04 - d0002_Rev1.00
Compare and Compare Negative.
CMP{cond} Rn, Operand2
CMN{cond} Rn, Operand2
where:
cond
Rn
Operand2 is a flexible second operand. See Section 3.3.3 (p. 38) for details of the options.
These instructions compare the value in a register with Operand2. They update the condition flags on
the result, but do not write the result to a register.
The CMP instruction subtracts the value of Operand2 from the value in Rn. This is the same as a SUBS
instruction, except that the result is discarded.
The CMN instruction adds the value of Operand2 to the value in Rn. This is the same as an ADDS
instruction, except that the result is discarded.
In these instructions:
• do not use PC
• Operand2 must not be SP.
These instructions update the N, Z, C and V flags according to the result.
Move and Move NOT.
MOV{S}{cond} Rd, Operand2
MOV{cond} Rd, #imm16
MVN{S}{cond} Rd, Operand2
CMP
CMN
CMPGT
is an optional condition code, see Section 3.3.7 (p. 43) .
is the register holding the first operand.
R2, R9
R0, #6400
SP, R7, LSL #2
...the world's most energy friendly microcontrollers
62
www.energymicro.com

Related parts for EFM32G200F16