EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 46
![MCU 32BIT 16KB FLASH 32-QFN](/photos/28/61/286134/32-qfn_sml.jpg)
EFM32G200F16
Manufacturer Part Number
EFM32G200F16
Description
MCU 32BIT 16KB FLASH 32-QFN
Manufacturer
Energy Micro
Series
Geckor
Datasheets
1.EFM32G200F16.pdf
(63 pages)
2.EFM32G200F16.pdf
(10 pages)
3.EFM32G200F16.pdf
(463 pages)
4.EFM32G200F16.pdf
(136 pages)
Specifications of EFM32G200F16
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 4x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
EFM32G200
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
- EFM32G200F16 PDF datasheet
- EFM32G200F16 PDF datasheet #2
- EFM32G200F16 PDF datasheet #3
- EFM32G200F16 PDF datasheet #4
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- Download datasheet (8Mb)
2010-09-06 - d0001_Rev1.00
alternate data structure. After this cycle completes, the controller performs another four DMA transfers
using the primary data structure. The controller continues to switch from primary to alternate to primary…
until either:
• the host processor configures the alternate data structure for a basic cycle
• it reads an invalid data structure.
The controller only asserts dma_done[C] when the scatter-gather transaction completes using an auto-
request cycle.
In scatter-gather mode, the controller uses the primary data structure to program the alternate data
structure. Table 8.4 (p. 46) lists the fields of the channel_cfg memory location for the primary data
structure, that you must program with constant values and those that can be user defined.
Table 8.4. channel_cfg for a primary data structure, in memory scatter-gather mode
1
that you must configure the alternate data structure.
See Section 8.4.3.3 (p. 53) for more information.
Figure 8.4 (p. 47) shows a memory scatter-gather example.
Because the R_power field is set to four, you must set N to be a multiple of four. The value given by N/4 is the number of times
Bit
Constant-value fields:
[31:30}
[29:28]
[27:26]
[25:24]
[17:14]
[3]
[2:0]
User defined values:
[23:21]
[20:18]
[13:4]
Note
Field
dst_inc
dst_size
src_inc
src_size
R_power
next_useburst
cycle_ctrl
dst_prot_ctrl
src_prot_ctrl
n_minus_1
After the controller completes the N primary transfers it invalidates the primary data
structure by setting the cycle_ctrl field to b000.
Value
b10
b10
b10
b10
b0010
0
b100
-
-
N
1
Description
Configures the controller to use word increments for the address
Configures the controller to use word transfers
Configures the controller to use word increments for the address
Configures the controller to use word transfers
Configures the controller to perform four DMA transfers
For a memory scatter-gather DMA cycle, this bit must be set to zero
Configures the controller to perform a memory scatter-gather DMA cycle
Configures the state of HPROT when the controller writes the destination data
Configures the state of HPROT when the controller reads the source data
Configures the controller to perform N DMA transfers, where N is a multiple of four
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46
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