SST89V54RD-33-C-PIE Microchip Technology, SST89V54RD-33-C-PIE Datasheet - Page 37

• Manufacturer Part Number: SST89V54RD-33-C-PIE
• Description: IC MCU 8BIT 24KB FLASH 40PDIP
• Manufacturer: Microchip Technology
• Series: FlashFlex®r

Specifications of SST89V54RD-33-C-PIE

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 32
• Eeprom Size: 8K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: SST89xxxRD
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FlashFlex MCU
SST89V54RD2/RD / SST89V58RD2/RD
TABLE
Note: DISIAPL pin in PLCC or TQFP will also disable IAP commands if it is externally pulled low when reset.
5.0 TIMERS/COUNTERS
5.1 Timers
The device has three 16-bit registers that can be used as
either timers or event counters. The three timers/counters
are denoted Timer 0 (T0), Timer 1 (T1), and Timer 2 (T2).
Each is designated a pair of 8-bit registers in the SFRs.
The pair consists of a most significant (high) byte and least
significant (low) byte. The respective registers are TL0,
TH0, TL1, TH1, TL2, and TH2.
5.2 Timer Set-up
Refer to Table 3-8 for TMOD, TCON, and T2CON registers
regarding timers T0, T1, and T2. The following tables pro-
vide TMOD values to be used to set up Timers T0, T1, and
T2.
Except for the baud rate generator mode, the values given
for T2CON do not include the setting of the TR2 bit. There-
fore, bit TR2 must be set separately to turn the timer on.
©2007 Silicon Storage Technology, Inc.
Operation
Chip-Erase
Block-Erase
Sector-Erase
Byte-Program
Byte-Verify (Read)
Prog-SB1
Prog-SB2
Prog-SB3
Prog-SC0
Prog-SC1
Enable-Clock-Double
1. SFCF[6]=1 enables IAP commands; SFCF[6]=0 disables IAP commands.
2. Interrupt/Polling enable for flash operation completion
3. Chip-Erase only functions in IAP mode when EA#=0 (external memory execution) and device is not in level 4 locking.
4. X can be V
5. AH = Address high order byte
6. AL = Address low order byte
7. DI = Data Input, DO = Data Output, all other values are in hex.
8. SFAH[7:5] = 111b selects Block 1, SFAH[7] = 0b selects Block 0
9. Instruction must be located in Block 1 or external code memory.
SFCM[7] = 1: Interrupt enable for flash operation completion
9
9
9
9
9
4-2: IAP Commands
3
0: polling enable for flash operation completion
IL
or V
8
IH
9
, but no other value.
1
SFCM [6:0]
0DH
0BH
0EH
0CH
01H
0FH
03H
05H
09H
09H
08H
2
SFDT [7:0]
37
AAH
AAH
AAH
AAH
AAH
AAH
DO
55H
55H
DI
X
TABLE
7
Used as
Timer
Used as
Counter
7
1. The Timer is turned ON/OFF by setting/clearing
2. The Timer is turned ON/OFF by the 1 to 0 transition
bit TR0 in the software.
on INT0# (P3.2) when TR0 = 1 (hardware control).
Mode
5-1: Timer/Counter 0
0
1
2
3
0
1
2
3
SFAH [7:0]
8-bit Auto-Reload
8-bit Auto-Reload
Two 8-bit Timers
Two 8-bit Timers
AAH
5AH
13-bit Timer
16-bit Timer
13-bit Timer
16-bit Timer
AH
55H
AH
AH
AH
X
Function
X
X
X
4
5
Control
Internal
S71255-10-000
00H
01H
02H
03H
04H
05H
06H
07H
SFAL [7:0]
TMOD
AL
AL
AL
1
X
X
X
X
X
X
X
X
Data Sheet
6
External
Control
T4-2.0 1255
T5-1.0 1255
0CH
0DH
08H
09H
0AH
0BH
0EH
0FH
12/07
2