ATTINY167-MU Atmel, ATTINY167-MU Datasheet - Page 11
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ATTINY167-MU
Manufacturer Part Number
ATTINY167-MU
Description
IC MCU AVR 16K FLASH 32VQFN 5X5
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY87-SU.pdf
(22 pages)
Specifications of ATTINY167-MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VFQFN Exposed Pad
Processor Series
ATtiny
Core
AVR
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, USI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
5
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 150 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
3. Instruction Set Summary
8265BS–AVR–09/10
Mnemonics
RCALL
BREQ
BRCC
BRGE
BRHC
ADIW
RJMP
ICALL
CPSE
SBRC
SBRS
BRBS
BRBC
BRNE
BRCS
BRSH
BRLO
BRPL
BRHS
BRTS
BRTC
BRVS
BRVC
SBIW
CALL
BRMI
BRLT
SUBI
SBCI
ANDI
COM
IJMP
RETI
SBIC
SBIS
BRIE
BRID
ADD
ADC
SUB
SBC
AND
EOR
NEG
SBR
CBR
DEC
CLR
SER
JMP
RET
CPC
TST
ORI
INC
CPI
SBI
CBI
LSL
OR
CP
Operands
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rdl,K
Rd, K
Rd, K
Rd, K
Rd, K
Rd,Rr
Rd,Rr
Rd,Rr
Rdl,K
Rd,K
Rd,K
Rd,K
Rr, b
Rr, b
P, b
P, b
s, k
s, k
Rd
Rd
Rd
Rd
Rd
Rd
Rd
P,b
P,b
Rd
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
Subtract with Carry Constant from Reg.
ARITHMETIC AND LOGIC INSTRUCTIONS
Logical AND Register and Constant
Branch if Greater or Equal, Signed
Logical OR Register and Constant
Compare Register with Immediate
Branch if Overflow Flag is Cleared
Branch if Less Than Zero, Signed
Subtract with Carry two Registers
Branch if Half Carry Flag Cleared
Skip if Bit in I/O Register Cleared
Subtract Constant from Register
Subtract Immediate from Word
Skip if Bit in I/O Register is Set
Branch if Overflow Flag is Set
Add with Carry two Registers
Skip if Bit in Register Cleared
Branch if Status Flag Cleared
Branch if Half Carry Flag Set
Branch if Interrupt Disabled
Skip if Bit in Register is Set
Branch if Interrupt Enabled
Branch if Same or Higher
Branch if Status Flag Set
Relative Subroutine Call
Branch if T Flag Cleared
Add Immediate to Word
Exclusive OR Registers
Branch if Carry Cleared
Clear Bit in I/O Register
Compare, Skip if Equal
Subtract two Registers
Logical AND Registers
Clear Bit(s) in Register
Test for Zero or Minus
Direct Subroutine Call
BIT AND BIT-TEST INSTRUCTIONS
Set Bit in I/O Register
Logical OR Registers
Set Bit(s) in Register
Compare with Carry
Branch if T Flag Set
One’s Complement
Indirect Jump to (Z)
Branch if Not Equal
Two’s Complement
Branch if Carry Set
Description
Add two Registers
Indirect Call to (Z)
Subroutine Return
Logical Shift Left
Interrupt Return
Branch if Lower
Branch if Equal
Branch if Minus
Clear Register
Relative Jump
Branch if Plus
Set Register
Direct Jump
Decrement
Increment
Compare
BRANCH INSTRUCTIONS
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
if (Rd = Rr) PC ← PC + 2 or 3
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
Rd(n+1) ← Rd(n), Rd(0) ← 0
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
Rdh:Rdl ← Rdh:Rdl + K
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • (0xFF - K)
Rd ← Rd + Rr + C
PC ← PC + k + 1
Rd ← Rd - Rr - C
Rd ← 0xFF − Rd
PC ← PC + k + 1
Rd ← 0x00 − Rd
Rd ← Rd - K - C
Operation
Rd ← Rd ⊕ Rd
Rd ← Rd ⊕ Rr
Rd ← Rd • Rd
Rd ← Rd + Rr
Rd ← Rd • Rr
Rd ← Rd v Rr
PC ← STACK
PC ← STACK
Rd ← Rd - Rr
Rd ← Rd • K
Rd ← Rd v K
Rd ← Rd v K
Rd ← Rd + 1
Rd ← Rd − 1
Rd ← Rd - K
I/O(P,b) ← 1
I/O(P,b) ← 0
Rd − Rr − C
Rd ← 0xFF
PC ← Z
PC ← Z
PC ← k
PC ← k
Rd − Rr
Rd − K
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,S
Flags
Z,C,N,V
Z,C,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
I
#Clock
1/2/3
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
3
3
4
4
4
1
1
1
2
2
1
11