AT89LP52-20JU Atmel, AT89LP52-20JU Datasheet - Page 42
![IC MCU 8051 8K FLASH SPI 44PLCC](/photos/39/69/396975/plcc-44_sml.jpg)
AT89LP52-20JU
Manufacturer Part Number
AT89LP52-20JU
Description
IC MCU 8051 8K FLASH SPI 44PLCC
Manufacturer
Atmel
Series
89LPr
Datasheet
1.AT89LP52-20MU.pdf
(113 pages)
Specifications of AT89LP52-20JU
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LCC (J-Lead)
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
Serial
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
36
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT89LP52-20JU
Manufacturer:
Atmel
Quantity:
110
10.1.3
42
AT89LP51/52 - Preliminary
Open-drain Output
Figure 10-1. Quasi-bidirectional Output
Figure 10-2. Input Only
Figure 10-3. Input Circuit for P3.2, P3.3, P4.6 and P4.7
The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor
of the port pin when the port latch contains a logic “0”. To be used as a logic output, a port con-
figured in this manner must have an external pull-up, typically a resistor tied to V
down for this mode is the same as for the quasi-bidirectional mode. The open-drain port configu-
ration is shown in
during Power-down (see
Power-down when configured in this mode.
Figure 10-4. Open-Drain Output
Register
F rom P o r t
F rom P o r t
Register
Figure
Figure
10-4. The input circuitry of P3.2, P3.3, P4.6 and P4.7 is not disabled
Input
Data
Input
Data
1 Clo c k Del a y
(D Flip-Flop)
10-3) and therefore these pins should not be left floating during
PWD
Input
Input
Data
Data
PWD
PWD
V
Strong
CC
P o r t
Port
Pin
Pin
V
W ea k
V e r y
CC
V
W ea k
CC
P o r t
Pin
3709B–MICRO–12/10
P o r t
Pin
DD
. The pull-