ATMEGA48PA-AN Atmel, ATMEGA48PA-AN Datasheet - Page 180
ATMEGA48PA-AN
Manufacturer Part Number
ATMEGA48PA-AN
Description
MCU AVR 4KB FLASH 20MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA48PA-AN.pdf
(448 pages)
Specifications of ATMEGA48PA-AN
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 180 of 448
- Download datasheet (13Mb)
19.3.3
19.3.4
19.4
8161D–AVR–10/09
Frame Formats
External Clock
Synchronous Clock Operation
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to
External clock input from the XCKn pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process intro-
duces a two CPU clock period delay and therefore the maximum external XCKn clock frequency
is limited by the following equation:
Note that f
add some margin to avoid possible loss of data due to frequency variations.
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxDn) is sampled at the
opposite XCKn clock edge of the edge the data output (TxDn) is changed.
Figure 19-3. Synchronous Mode XCKn Timing.
The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is
used for data change. As
rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data will be changed
at falling XCKn edge and sampled at rising XCKn edge.
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of
the following as valid frame formats:
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
UCPOL = 1
UCPOL = 0
osc
depends on the stability of the system clock source. It is therefore recommended to
Figure 19-2
RxD / TxD
RxD / TxD
XCK
XCK
Figure 19-3
for details.
ATmega48PA/88PA/168PA/328P
shows, when UCPOLn is zero the data will be changed at
f
XCK
<
f
---------- -
OSC
4
Sample
Sample
180
Related parts for ATMEGA48PA-AN
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IC AVR MCU 4K 5V 20MHZ 32-TQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
Manufacturer:
Atmel Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Atmel Corporation
Datasheet:
Part Number:
Description:
IC AVR MCU 4K 20MHZ 5V 32TQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC AVR MCU 4K 20MHZ 5V 28DIP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC AVR MCU 4K 20MHZ 5V 32-QFN
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC AVR MCU 4K 5V 20MHZ 32-TQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC AVR MCU 4K 5V 20MHZ 32-QFN
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC AVR MCU 4K 5V 20MHZ 32-QFN
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC AVR MCU 4K 5V 20MHZ 28-DIP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC AVR MCU 4K 5V 20MHZ 28-DIP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
IC AVR MCU 4K FLASH 20MHZ 28QFN
Manufacturer:
Atmel
Datasheet: