M054ZAN Nuvoton Technology Corporation of America, M054ZAN Datasheet - Page 170
M054ZAN
Manufacturer Part Number
M054ZAN
Description
IC MCU 32BIT 16KB FLASH 33QFN
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro M051™r
Specifications of M054ZAN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 5x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
33-WFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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[4]
[3]
[2]
[1:0]
NuMicro M051
STO
SI
AA
Reserved
I2C STOP Control Bit
In master mode, setting STO to transmit a STOP condition to bus then I2C
hardware will check the bus condition if a STOP condition is detected this
bit will be cleared by hardware automatically. In a slave mode, setting STO
resets I2C hardware to the defined “not addressed” slave mode. This
means it is NO LONGER in the slave receiver mode to receive data from
the master transmit device.
I2C Interrupt Flag
When a new SIO state is present in the I2CSTATUS register, the SI flag is
set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is
requested. SI must be cleared by software. Clear SI is by writing one to this
bit.
Assert Acknowledge Control Bit
When AA=1 prior to address or data received, an acknowledged (low level
to SDA) will be returned during the acknowledge clock pulse on the SCL
line when 1.) A slave is acknowledging the address sent from master, 2.)
The receiver devices are acknowledging the data sent by transmitter. When
AA=0 prior to address or data received, a Not acknowledged (high level to
SDA) will be returned during the acknowledge clock pulse on the SCL line.
Reserved
™
Series Technical Reference Manual
- 170 -
Publication Release Date: Sep 14, 2010
Revision V1.2
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