M052LAN Nuvoton Technology Corporation of America, M052LAN Datasheet - Page 238

• Manufacturer Part Number: M052LAN
• Description: IC MCU 32BIT 8KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro M051™r

Specifications of M052LAN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

™
NuMicro M051
Series Technical Reference Manual
Variable Serial Clock Frequency
In master mode, the output of serial clock can be programmed as variable frequency pattern if the
Variable Clock Enable bit VARCLK_EN (SPI_CNTRL [23]) is enabled. The frequency pattern
format is defined in VARCLK (SPI_VARCLK [31:0]) register. If the bit content of VARCLK is ‘0’ the
output frequency is according with the DIVIDER (SPI_DIVIDER[15:0]) and if the bit content of
VARCLK is ‘1’, the output frequency is according to the DIVIDER2 (SPI_DIVIDER[31:16]). The
Figure 6.7-7 is the timing relationship among the serial clock (SPICLK), the VARCLK, the
DIVIDER and the DIVIDER2 registers. A two-bit combination in the VARCLK defines one clock
cycle. The bit field VARCLK [31:30] defines the first clock cycle of SPICLK. The bit field VARCLK
[29:28] defines the second clock cycle of SPICLK and so on. The clock source selections are
defined in VARCLK and it must be set 1 cycle before the next clock option. For example, if there
are 5 CLK1 cycle in SPICLK, the VARCLK shall set 9 ‘0’ in the MSB of VARCLK. The 10th shall
be set as ‘1’ in order to switch the next clock source is CLK2. Note that when enable the
VARCLK_EN bit, the setting of TX_BIT_LEN must be programmed as 0x10 (16 bits mode only).
Figure 6.7-7 Variable Serial Clock Frequency
Publication Release Date: Sep 14, 2010
- 238 -
Revision V1.2