NUC100RD2BN Nuvoton Technology Corporation of America, NUC100RD2BN Datasheet - Page 2

IC MCU 32BIT 64KB FLASH 64LQFP

NUC100RD2BN

Manufacturer Part Number
NUC100RD2BN
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Datasheets

Specifications of NUC100RD2BN

Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
49
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NUC100RD2BN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
1.
GPIO
UART
EBI
High performance mode
2.
The above information is the exclusive intellectual property of Nuvoton Technology and shall not be disclosed, distributed or reproduced without
The different features list:
The part number and alternate replacement part number list:
NUC100RD1AN
NUC100RD2AN
NUC120RD1AN
NUC120RD2AN
NUC100LC1AN
NUC100LD1AN
NUC100LD2AN
NUC100RC1AN
NUC120LC1AN
NUC120LD1AN
NUC120LD2AN
NUC120RC1AN
Item
Part number
-
-
NUC100LD2AN, NUC100RC1AN,
NUC100RD1AN, NUC100RD2AN,
NUC120LD2AN, NUC120RC1AN,
NUC100LC1AN, NUC100LD1AN,
NUC120LC1AN, NUC120LD1AN,
NUC120RD1AN, NUC120RD2AN
Max. GPIO toggle cycle is 7 HCLK
Did not support this feature.
Alternate Replacement P/N
NUC100LC1BN
NUC100LD1BN
NUC100LD2BN
NUC100RC1BN
NUC100RD1BN
NUC100RD2BN
NUC120LC1BN
NUC120LD1BN
NUC120LD2BN
NUC120RC1BN
NUC120RD1BN
NUC120RD2BN
permission from Nuvoton.
Appendix
表單編號 : 1110-0001-08-A
Add RS485 mode
Support 8/16-bit bus width and byte write for
16-bit data bus width
Only 64-pin package with EBI function
HPMEN bit in CPR0[0] (@0x50000010) is
used to enable flash sequential address code
fetch, SRAM read access and GPIO pin toggle
speed improvement logic.
HPMEN=0, flash controller, SRAM read
access, and GPIO pin toggle behavior are fully
compatible with NUC1XXAN.
HPMEN=1, CPU performance is improved
about 10% and GPIO pin toggle cycles is
improved from 7 HCLK to 4 HCLK.
Max. GPIO toggle cycle is improved from 7
HCLK to 4 HCLK.
Add single bit control, all pin can be
read/write individually.
NUC100RD1BN, NUC100RD2BN,
NUC100LC1BN, NUC100LD1BN,
NUC100LD2BN, NUC100RC1BN,
NUC120LC1BN, NUC120LD1BN,
NUC120LD2BN, NUC120RC1BN,
NUC120RD1BN, NUC120RD2BN

Related parts for NUC100RD2BN