XC6VLX760-L1FF1760I Xilinx Inc, XC6VLX760-L1FF1760I Datasheet
XC6VLX760-L1FF1760I
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XC6VLX760-L1FF1760I Summary of contents
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DS150 (v2.2) January 28, 2010 General Description The Virtex®-6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to ...
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... XC6VLX130T 128,000 20,000 1,740 XC6VLX195T 199,680 31,200 3,040 XC6VLX240T 241,152 37,680 3,650 XC6VLX365T 364,032 56,880 4,130 XC6VLX550T 549,888 85,920 6,200 XC6VLX760 758,784 118,560 8,280 XC6VSX315T 314,880 49,200 5,090 XC6VSX475T 476,160 74,400 7,640 XC6VHX250T 251,904 39,360 3,040 XC6VHX255T 253,440 39,600 3,050 XC6VHX380T 382,464 ...
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... XC6VLX130T 8 240 XC6VLX195T XC6VLX240T XC6VLX365T XC6VLX550T XC6VLX760 XC6VSX315T XC6VSX475T Notes: 1. Flip-chip packages are also available in Pb-Free versions (FFG). Virtex-6 HXT FPGA package combinations with the maximum available I/Os per package are shown in Table 3: Virtex-6 HXT FPGA Device-Package Combinations and Maximum Available I/Os ...
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Configuration Virtex-6 FPGAs store their customized configuration in SRAM-type internal latches. The number of configuration bits is between 26 Mb and 160 MB), depending on device size but independent of the specific user-design implementation, unless compression ...
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Clock Management Each Virtex-6 FPGA has up to nine clock management tiles (CMTs), each consisting of two mixed-mode clock managers (MMCMs), which are PLL based. Phase-Locked Loop The MMCM can serve as a frequency synthesizer for a wider range of ...
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Block RAM Every Virtex-6 FPGA has between 156 and 1064 dual-port block RAMs, each storing 36 Kbits. Each block RAM has two completely independent ports that share nothing but the stored data. Synchronous Operation Each memory access, read and write, ...
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Input/Output The number of I/O pins varies from 240 to 1200 depending on device and package size. Each I/O pin is configurable and can comply with a large number of standards, using up to 2.5V. The Virtex-6 FPGA SelectIO Resources ...
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... PCI Express devices. All Virtex-6 devices (except the XC6VLX760) include at least one integrated interface block for PCI Express technology that can be configured as an Endpoint or Root Port, compliant to the PCI Express Base Specification Revision 2.0. The Root Port can be used to build the basis for a compatible Root Complex, to allow custom FPGA-FPGA communication via the PCI Express protocol, and to attach ASSP Endpoint devices such as Fibre Channel HBAs to the FPGA ...
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... SelectIO resources. This TEMAC block saves logic resources and design effort. All of the Virtex-6 devices (except the XC6VLX760) have four TEMAC blocks, implementing the link layer of the OSI protocol stack. The CORE Generator™ software GUI helps to configure flexible interfaces to GTX transceiver or SelectIO technology, to the FPGA logic, and to a microprocessor (when required) ...
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Revision History The following table shows the revision history for this document: Date Version 02/02/09 1.0 Initial Xilinx release. 05/05/09 1.1 Added the FF1156 package for both the XC6VSX315T and XC6VSX475T devices in Updated the PCI Express design discussion on ...
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... Advance Product Specification Virtex-6 FPGA GTX Transceivers User Guide (UG366) This guide describes the GTX transceivers available in all the Virtex-6 FPGAs except the XC6VLX760. Virtex-6 FPGA GTH Transceivers User Guide (UG371) This guide describes the GTH transceivers available in all Virtex-6 HXT FPGAs except the XC6VHX250T and the XC6VHX380T in the FF1154 package ...