XC2V6000-5FF1517I Xilinx Inc, XC2V6000-5FF1517I Datasheet - Page 27
![no-image](/images/no-image-200.jpg)
XC2V6000-5FF1517I
Manufacturer Part Number
XC2V6000-5FF1517I
Description
IC FPGA VIRTEX-II 1517FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-IIr
Datasheet
1.XC2V250-4FGG256C.pdf
(318 pages)
Specifications of XC2V6000-5FF1517I
Number Of Labs/clbs
8448
Total Ram Bits
2654208
Number Of I /o
1104
Number Of Gates
6000000
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1517-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Logic Elements/cells
-
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Sum of Products
Each Virtex-II slice has a dedicated OR gate named ORCY,
ORing together outputs from the slices carryout and the ORCY
from an adjacent slice. The ORCY gate with the dedicated
Sum of Products (SOP) chain are designed for implementing
LUTs and MUXCYs can implement large AND gates or
other combinatorial logic functions.
DS031-2 (v3.5) November 5, 2007
Product Specification
4
4
4
4
R
LUT
LUT
LUT
LUT
4
4
4
4
MUXCY
MUXCY
MUXCY
MUXCY
ORCY
Slice 1
Slice 0
V
CC
4
4
4
4
LUT
LUT
LUT
LUT
Figure 26: Wide-Input AND Gate (16 Inputs)
LUT
LUT
LUT
LUT
Figure 26
Figure 25: Horizontal Cascade Chain
MUXCY
MUXCY
MUXCY
MUXCY
ORCY
Slice 2
Slice 3
V
illustrates
CC
“0”
“0”
“0”
CLB
0
0
0
0
MUXCY
MUXCY
MUXCY
MUXCY
www.xilinx.com
V CC
1
1
1
1
4
4
4
4
Slice
Slice
large, flexible SOP chains. One input of each ORCY is con-
nected through the fast SOP chain to the output of the previous
ORCY in the same slice row. The second input is connected to
the output of the top MUXCY in the same slice, as shown in
Figure
LUT and MUXCY resources configured as a 16-input AND
gate.
LUT
LUT
LUT
LUT
OUT
25.
Virtex-II Platform FPGAs: Functional Description
MUXCY
MUXCY
MUXCY
MUXCY
ORCY
Slice 0
Slice 1
V
CC
16
4
4
4
4
LUT
LUT
LUT
LUT
AND
DS031_41_110600
MUXCY
MUXCY
MUXCY
MUXCY
OUT
ORCY
Slice 3
Slice 2
V
CC
CLB
ds031_64_110300
SOP
Module 2 of 4
19
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