XC6VHX250T-2FF1154I Xilinx Inc, XC6VHX250T-2FF1154I Datasheet
XC6VHX250T-2FF1154I
Specifications of XC6VHX250T-2FF1154I
Available stocks
Related parts for XC6VHX250T-2FF1154I
XC6VHX250T-2FF1154I Summary of contents
Page 1
DS150 (v2.2) January 28, 2010 General Description The Virtex®-6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to ...
Page 2
... XC6VLX550T 549,888 85,920 6,200 XC6VLX760 758,784 118,560 8,280 XC6VSX315T 314,880 49,200 5,090 XC6VSX475T 476,160 74,400 7,640 XC6VHX250T 251,904 39,360 3,040 XC6VHX255T 253,440 39,600 3,050 XC6VHX380T 382,464 59,760 4,570 XC6VHX565T 566,784 88,560 6,370 Notes: 1. Each Virtex-6 FPGA slice contains four LUTs and eight flip-flops, only some slices can use their LUTs as distributed RAM or SRLs. ...
Page 3
... Virtex-6 HXT FPGA package combinations with the maximum available I/Os per package are shown in Table 3: Virtex-6 HXT FPGA Device-Package Combinations and Maximum Available I/Os FF1154 Package FFG1154 Size (mm Device GTXs GTHs XC6VHX250T 48 XC6VHX255T XC6VHX380T 48 XC6VHX565T Notes: 1. Flip-chip packages are also available in Pb-Free versions (FFG). DS150 (v2.2) January 28, 2010 ...
Page 4
Configuration Virtex-6 FPGAs store their customized configuration in SRAM-type internal latches. The number of configuration bits is between 26 Mb and 160 MB), depending on device size but independent of the specific user-design implementation, unless compression ...
Page 5
Clock Management Each Virtex-6 FPGA has up to nine clock management tiles (CMTs), each consisting of two mixed-mode clock managers (MMCMs), which are PLL based. Phase-Locked Loop The MMCM can serve as a frequency synthesizer for a wider range of ...
Page 6
Block RAM Every Virtex-6 FPGA has between 156 and 1064 dual-port block RAMs, each storing 36 Kbits. Each block RAM has two completely independent ports that share nothing but the stored data. Synchronous Operation Each memory access, read and write, ...
Page 7
Input/Output The number of I/O pins varies from 240 to 1200 depending on device and package size. Each I/O pin is configurable and can comply with a large number of standards, using up to 2.5V. The Virtex-6 FPGA SelectIO Resources ...
Page 8
The System Monitor does not require explicit instantiation in a design. Once the appropriate power supply connections are made, measurement data can be accessed at any time, even pre-configuration or during power down, through the JTAG test access port (TAP). ...
Page 9
This block is highly configurable to system design requirements and can operate lanes at the 2.5 Gb/s data rate and the 5.0 Gb/s data rate. For high-performance applications, advanced buffering techniques of the block offer ...
Page 10
Revision History The following table shows the revision history for this document: Date Version 02/02/09 1.0 Initial Xilinx release. 05/05/09 1.1 Added the FF1156 package for both the XC6VSX315T and XC6VSX475T devices in Updated the PCI Express design discussion on ...
Page 11
... Virtex-6 FPGAs except the XC6VLX760. Virtex-6 FPGA GTH Transceivers User Guide (UG371) This guide describes the GTH transceivers available in all Virtex-6 HXT FPGAs except the XC6VHX250T and the XC6VHX380T in the FF1154 package. Virtex-6 FPGA DSP48E1 Slice User Guide (UG369) This guide describes the architecture of the DSP48E1 slice in Virtex-6 FPGAs and provides configuration examples ...