XC2V2000-4BF957I Xilinx Inc, XC2V2000-4BF957I Datasheet - Page 5

• Manufacturer Part Number: XC2V2000-4BF957I
• Description: IC FPGA VIRTEX-II 957FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V2000-4BF957I

• Number Of Labs/clbs: 2688
• Total Ram Bits: 1032192
• Number Of I /o: 624
• Number Of Gates: 2000000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 957-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -

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The digitally controlled impedance (DCI) I/O feature auto-
matically provides on-chip termination for each I/O element.
The IOB elements also support the following differential sig-
naling I/O standards:
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Two adjacent pads are used for each differential pair. Two or
four IOB blocks connect to one switch matrix to access the
routing resources.
Configurable Logic Blocks (CLBs)
CLB resources include four slices and two 3-state buffers.
Each slice is equivalent and contains:
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The function generators F & G are configurable as 4-input
look-up tables (LUTs), as 16-bit shift registers, or as 16-bit
distributed SelectRAM memory.
In addition, the two storage elements are either edge-trig-
gered D-type flip-flops or level-sensitive latches.
Each CLB has internal fast interconnect and connects to a
switch matrix to access general routing resources.
Block SelectRAM Memory
The block SelectRAM memory resources are 18 Kb of
dual-port RAM, programmable from 16K x 1 bit to 512 x 36
bits, in various depth and width configurations. Each port is
totally synchronous and independent, offering three
"read-during-write" modes. Block SelectRAM memory is
cascadable to implement large embedded storage blocks.
Supported memory configurations for dual-port and sin-
gle-port modes are shown in
Table 3: Dual-Port And Single-Port Configurations
DS031-1 (v3.5) November 5, 2007
Product Specification
HSTL (Class I, II, III, and IV)
SSTL (3.3V and 2.5V, Class I and II)
AGP-2X
LVDS
BLVDS (Bus LVDS)
ULVDS
LDT
LVPECL
Two function generators (F & G)
Two storage elements
Arithmetic logic gates
Large multiplexers
Wide function capability
Fast carry look-ahead chain
Horizontal cascade chain (OR gate)
16K x 1 bit
8K x 2 bits
4K x 4 bits
R
Table
3.
512 x 36 bits
1K x 18 bits
2K x 9 bits
www.xilinx.com
A multiplier block is associated with each SelectRAM mem-
ory block. The multiplier block is a dedicated 18 x 18-bit
multiplier and is optimized for operations based on the block
SelectRAM content on one port. The 18 x 18 multiplier can
be used independently of the block SelectRAM resource.
Read/multiply/accumulate operations and DSP filter struc-
tures are extremely efficient.
Both the SelectRAM memory and the multiplier resource
are connected to four switch matrices to access the general
routing resources.
Global Clocking
The DCM and global clock multiplexer buffers provide a
complete solution for designing high-speed clocking
schemes.
Up to 12 DCM blocks are available. To generate de-skewed
internal or external clocks, each DCM can be used to elimi-
nate clock distribution delay. The DCM also provides 90-,
180-, and 270-degree phase-shifted versions of its output
clocks. Fine-grained phase shifting offers high-resolution
phase adjustments in increments of 1/256 of the clock
period. Very flexible frequency synthesis provides a clock
output frequency equal to any M/D ratio of the input clock
frequency, where M and D are two integers. For the exact
timing parameters, see
Virtex-II devices have 16 global clock MUX buffers, with up
to eight clock nets per quadrant. Each global clock MUX
buffer can select one of the two clock inputs and switch
glitch-free from one clock to the other. Each DCM block is
able to drive up to four of the 16 global clock MUX buffers.
Routing Resources
The IOB, CLB, block SelectRAM, multiplier, and DCM ele-
ments all use the same interconnect scheme and the same
access to the global routing matrix. Timing models are
shared, greatly improving the predictability of the perfor-
mance of high-speed designs.
There are a total of 16 global clock lines, with eight available
per quadrant. In addition, 24 vertical and horizontal long
lines per row or column as well as massive secondary and
local routing resources provide fast interconnect. Virtex-II
buffered interconnects are relatively unaffected by net
fanout and the interconnect layout is designed to minimize
crosstalk.
Horizontal and vertical routing resources for each row or
column include:
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Virtex-II Platform FPGAs: Introduction and Overview
24 long lines
120 hex lines
40 double lines
16 direct connect lines (total in all four directions)
Virtex-II Electrical
Characteristics.
Module 1 of 4
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