XC3S1600E-4FG400I Xilinx Inc, XC3S1600E-4FG400I Datasheet - Page 64

• Manufacturer Part Number: XC3S1600E-4FG400I
• Description: IC FPGA SPARTAN 3E 400FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S1600E-4FG400I

• Number Of Logic Elements/cells: 33192
• Number Of Labs/clbs: 3688
• Total Ram Bits: 663552
• Number Of I /o: 304
• Number Of Gates: 1600000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Functional Description
Interconnect
For additional information, refer to the Using Interconnect
chapter in UG331.
Interconnect is the programmable network of signal path-
ways between the inputs and outputs of functional elements
within the FPGA, such as IOBs, CLBs, DCMs, and block
RAM.
Overview
Interconnect, also called routing, is segmented for optimal
connectivity. Functionally, interconnect resources are identi-
cal to that of the Spartan-3 architecture. There are four
kinds of interconnects: long lines, hex lines, double lines,
and direct lines. The Xilinx Place and Route (PAR) software
exploits the rich interconnect array to deliver optimal system
performance and the fastest compile times.
64
Figure 48: Four Types of Interconnect Tiles (CLBs, IOBs, DCMs, and Block RAM/Multiplier)
Switch
Switch
Switch
Matrix
Matrix
Matrix
DCM
CLB
IOB
www.xilinx.com
Switch
Switch
Switch
Switch
Matrix
Matrix
Matrix
Matrix
Switch Matrix
The switch matrix connects to the different kinds of intercon-
nects across the device. An interconnect tile, shown in
Figure
a functional element, such as a CLB, IOB, or DCM. If a func-
tional element spans across multiple switch matrices such
as the block RAM or multipliers, then an interconnect tile is
defined by the number of switch matrices connected to that
functional element. A Spartan-3E device can be repre-
sented as an array of interconnect tiles where interconnect
resources are for the channel between any two adjacent
interconnect tile rows or columns as shown in
48, is defined as a single switch matrix connected to
Block
18Kb
RAM
DS312_08_020905
18 x 18
MULT
DS312-2 (v3.8) August 26, 2009
Product Specification
Figure
49.
R