XA6SLX9-2CSG324Q Xilinx Inc, XA6SLX9-2CSG324Q Datasheet - Page 5

• Manufacturer Part Number: XA6SLX9-2CSG324Q
• Description: IC FPGA SPARTAN 6 324CSGBGA
• Manufacturer: Xilinx Inc
• Series: Spartan®-6r

Specifications of XA6SLX9-2CSG324Q

• Number Of Logic Elements/cells: 9152
• Number Of Labs/clbs: 715
• Total Ram Bits: 589824
• Number Of I /o: 200
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-LFBGA, CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Clock Distribution
Each XA Spartan-6 FPGA provides abundant clock lines to address the different clocking requirements of high fanout, short
propagation delay, and extremely low skew.
Global Clock Lines
In each XA Spartan-6 FPGA, 16 global-clock lines have the highest fanout and can reach every flip-flop clock. Global clock
lines must be driven by global clock buffers, which can also perform glitchless clock multiplexing and the clock enable
function. Global clocks are often driven from the CMTs, which can completely eliminate the basic clock distribution delay.
I/O Clocks
I/O clocks are especially fast and serve only the localized input and output delay circuits and the I/O serializer/deserializer
(SERDES) circuits, as described in the
Block RAM
Every XA Spartan-6 FPGA has between 12 and 172 dual-port block RAMs, each storing 18 Kb. Each block RAM has two
completely independent ports that share only the stored data.
Synchronous Operation
Each memory access, whether read or write, is controlled by the clock. All inputs, data, address, clock enables, and write
enables are registered. The data output is always latched, retaining data until the next operation. An optional output data
pipeline register allows higher clock rates at the cost of an extra cycle of latency.
During a write operation in dual-port mode, the data output can reflect either the previously stored data, the newly written
data, or remain unchanged.
Programmable Data Width
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Memory Controller Block
Most XA Spartan-6 devices include dedicated memory controller blocks (MCBs), each targeting a single-chip DRAM (either
DDR, DDR2, DDR3, or LPDDR), and supporting access rates of up to 800 Mb/s.
The MCB has dedicated routing to predefined FPGA I/Os. If the MCB is not used, these I/Os are available as general
purpose FPGA I/Os. The memory controller offers a complete multi-port arbitrated interface to the logic inside the XA
Spartan-6 FPGA. Commands can be pushed, and data can be pushed to and pulled from independent built-in FIFOs, using
conventional FIFO control signals. The multi-port memory controller can be configured in many ways. An internal 32-, 64-,
or 128-bit data interface provides a simple and reliable interface to the MCB.
The MCB can be connected to 4-, 8-, or 16-bit external DRAM. The MCB, in many applications, provides a faster DRAM
interface compared to traditional internal data buses, which are wider and are clocked at a lower frequency. The FPGA logic
interface can be flexibly configured irrespective of the physical memory device.
DS170 (v1.0) March 2, 2010
Advance Product Specification
Each port can be configured as 16K × 1, 8K × 2, 4K × 4, 2K × 9 (or 8), 1K × 18 (or 16), or 512 x 36 (or 32).
The x9, x18, and x36 configurations include parity bits. The two ports can have different aspect ratios.
Each block RAM can be divided into two completely independent 9 Kb block RAMs that can each be configured to any
aspect ratio from 8K x 1 to 256 x 36.
In 9 Kb block RAMs, only simple dual-port mode can provide data widths of >18 bits. In this mode, one port is
dedicated to read operation and the other port is dedicated to write operation. The full freedom to mix port data width
values is retained, but there is no read output during write. The 18 Kb RAM has no dual-port data width limitation.
I/O Logic
section.
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XA Spartan-6 Automotive FPGA Family Overview
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