AD5235BRU25-RL7 Analog Devices Inc, AD5235BRU25-RL7 Datasheet - Page 17

• Manufacturer Part Number: AD5235BRU25-RL7
• Description: IC DGTL POT DUAL 1024POS 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5235BRU25-RL7

• Rohs Status: RoHS non-compliant
• Taps: 1024
• Resistance (ohms): 25K
• Number Of Circuits: 2
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 3 V ~ 5.5 V, ±2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Number Of Elements: 2
• # Of Taps: 1024
• Resistance (max): 25KOhm
• Power Supply Requirement: Single/Dual
• Interface Type: Serial (4-Wire/SPI)
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): ±2.5V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): ±2.25V
• Dual Supply Voltage (max): ±2.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Not Compliant
• Other names: AD5235BRU25-RL7; AD5235BRU25-RL7TR

EEMEM PROTECTION
The write protect ( WP ) pin disables any changes to the
scratchpad register contents, except for the EEMEM setting,
which can still be restored using Instruction 1, Instruction 8,
and the PR pulse. Therefore, WP can be used to provide a
hardware EEMEM protection feature.
DIGITAL INPUT AND OUTPUT CONFIGURATION
All digital inputs are ESD protected, high input impedance that
can be driven directly from most digital sources. Active at logic
low, PR and WP must be tied to V
internal pull-up resistors are present on any digital input pins.
To avoid floating digital pins that might cause false triggering
in a noisy environment, add pull-up resistors. This is applicable
when the device is detached from the driving source when it is
programmed.
The SDO and RDY pins are open-drain digital outputs that only
need pull-up resistors if these functions are used. To optimize
the speed and power trade-off, use 2.2 kΩ pull-up resistors.
The equivalent serial data input and output logic is shown in
Figure 38. The open-drain output SDO is disabled whenever
chip-select ( CS ) is in logic high. ESD protection of the digital
inputs is shown in
CLK
SDI
CS
Figure 38. Equivalent Digital Input and Output Logic
LOGIC
Figure 39. Equivalent ESD Digital Input Protection
PINS
COUNTER
COMMAND
Figure 39
VALID
REGISTER
and
SERIAL
INPUTS
300Ω
AND ADDRESS
AD5235
PROCESSOR
PR
COMMAND
Figure 40
DECODE
DD
, if they are not used. No
WP
.
GND
V
DD
SDO
GND
5V
(FOR DAISY
CHAIN ONLY)
R
PULL-UP
Rev. D | Page 17 of 32
SERIAL DATA INTERFACE
The AD5235 contains a 4-wire SPI-compatible digital interface
(SDI, SDO, CS , and CLK). The 24-bit serial data-word must be
loaded with MSB first. The format of the word is shown in
The command bits (C0 to C3) control the operation of the digital
potentiometer according to the command shown in
to A3 are the address bits. A0 is used to address RDAC1 or RDAC2.
Address 2 to Address 14 are accessible by users for extra EEMEM.
Address 15 is reserved for factory usage.
address map of the EEMEM locations. D0 to D9 are the values
for the RDAC registers. D0 to D15 are the values for the EEMEM
registers.
The AD5235 has an internal counter that counts a multiple of
24 bits (a frame) for proper operation. For example, AD5235
works with a 24-bit or 48-bit word, but it cannot work properly
with a 23-bit or 25-bit word. To prevent data from mislocking
(due to noise, for example), the counter resets, if the count is not a
multiple of four when CS goes high but remains in the register if it
is multiple of four. In addition, the AD5235 has a subtle feature
that, if CS is pulsed without CLK and SDI, the part repeats the
previous command (except during power-up). As a result, care
must be taken to ensure that no excessive noise exists in the CLK or
CS line that might alter the effective number-of-bits pattern.
The SPI interface can be used in two slave modes: CPHA = 1,
CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer
to the control bits that dictate SPI timing in the following
MicroConverters® and microprocessors: ADuC812, ADuC824,
M68HC11, MC68HC16R1, and MC68HC916R1.
WP
Figure 40. Equivalent WP Input Protection
INPUT
300 Ω
GND
V
DD
Table 9
provides an
AD5235
Table 7
Table 6
. A0
.