AD5235BRU25-RL7 Analog Devices Inc, AD5235BRU25-RL7 Datasheet - Page 16

• Manufacturer Part Number: AD5235BRU25-RL7
• Description: IC DGTL POT DUAL 1024POS 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5235BRU25-RL7

• Rohs Status: RoHS non-compliant
• Taps: 1024
• Resistance (ohms): 25K
• Number Of Circuits: 2
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 3 V ~ 5.5 V, ±2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Number Of Elements: 2
• # Of Taps: 1024
• Resistance (max): 25KOhm
• Power Supply Requirement: Single/Dual
• Interface Type: Serial (4-Wire/SPI)
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): ±2.5V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): ±2.25V
• Dual Supply Voltage (max): ±2.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Not Compliant
• Other names: AD5235BRU25-RL7; AD5235BRU25-RL7TR

AD5235
When two AD5235s are daisy-chained, 48 bits of data are
required. The first 24 bits (formatted 4-bit command, 4-bit
address, and 16-bit data) go to U2, and the second 24 bits with
the same format go to U1. Keep CS low until all 48 bits are
clocked into their respective serial registers. CS is then pulled
high to complete the operation.
TERMINAL VOLTAGE OPERATING RANGE
The positive V
define the boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on Terminal A,
Terminal B, and Terminal W that exceed V
the internal forward-biased diodes (see Figure 40).
The GND pin of the AD5235 is primarily used as a digital
ground reference. To minimize the digital ground bounce,
the AD5235 ground terminal should be joined remotely to
the common ground (see Figure 41). The digital input control
signals to the AD5235 must be referenced to the device ground
pin (GND) and must satisfy the logic level defined in the
Specifications section. An internal level-shift circuit ensures
that the common-mode voltage range of the three terminals
extends from V
CONTROLLER
MICRO-
SCLK SS
Figure 40. Maximum Terminal Voltages Set by V
MOSI
Figure 39. Daisy-Chain Configuration Using SDO
DD
SS
and negative V
to V
DD
SDI
CS
AD5235
, regardless of the digital input level.
U2
CLK
SDO
SS
power supplies of the AD5235
V
DD
2.2kΩ
R
P
DD
or V
SDI
CS
AD5235
SS
DD
V
V
A
W
B
are clamped by
U2
SS
and V
DD
CLK
SDO
SS
Rev. C | Page 16 of 28
Power-Up Sequence
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 40), it is
important to power V
voltage to Terminal A, Terminal B, and Terminal W. Otherwise,
the diode is forward-biased such that V
unintentionally. For example, applying 5 V across Terminal A
and Terminal B prior to V
4.3 V. It is not destructive to the device, but it might affect the
rest of the user’s system. The ideal power-up sequence is GND,
V
powering V
long as they are powered after V
Regardless of the power-up sequence and the ramp rates of the
power supplies, when V
preset activates, which restores the EEMEM values to the RDAC
registers.
Layout and Power Supply Bypassing
It is a good practice to employ compact, minimum lead-length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is good practice to bypass the power supplies with
quality capacitors for optimum stability. Bypass supply leads to
the device with 0.01 μF to 0.1 μF disk or chip ceramic capacitors.
Also, apply low ESR, 1 μF to 10 μF tantalum or electrolytic
capacitors at the supplies to minimize any transient disturbance
(see Figure 41).
DD
and V
SS
V
V
A
, digital inputs, and V
DD
SS
, V
10µF
10µF
B
, V
C3
C4
Figure 41. Power Supply Bypassing
W
, and the digital inputs is not important as
+
+
DD
0.1µF
0.1µF
DD
C1
C2
and V
DD
and V
causes the V
SS
DD
first before applying any
SS
A
and V
, V
are powered, the power-on
V
V
DD
SS
B
DD
, and V
AD5235
SS
GND
and V
DD
.
terminal to exhibit
W
SS
. The order of
are powered