PIC18LF24K22-I/SP Microchip Technology, PIC18LF24K22-I/SP Datasheet - Page 115
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PIC18LF24K22-I/SP
Manufacturer Part Number
PIC18LF24K22-I/SP
Description
IC PIC MCU 16KB FLASH 28SPDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18LF24K22-I/SP
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
64MHz
No. Of Timers
7
Processor Series
PIC18LF
Core
PIC
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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9.4
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
REGISTER 9-1:
2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
GIE/GIEH
R/W-0
2:
INTCON Registers
A mismatch condition will continue to set the RBIF bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
RB port change interrupts also require the individual pin IOCB enables.
GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts including peripherals
When IPEN = 1:
1 = Enables all high priority interrupts
0 = Disables all interrupts including low priority
PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low priority interrupts
0 = Disables all low priority interrupts
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
RBIE: Port B Interrupt-On-Change (IOCx) Interrupt Enable bit
1 = Enables the IOCx port change interrupt
0 = Disables the IOCx port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared by software)
0 = TMR0 register did not overflow
INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared by software)
0 = The INT0 external interrupt did not occur
RBIF: Port B Interrupt-On-Change (IOCx) Interrupt Flag bit
1 = At least one of the IOC<3:0> (RB<7:4>) pins changed state (must be cleared by software)
0 = None of the IOC<3:0> (RB<7:4>) pins have changed state
PEIE/GIEL
R/W-0
INTCON: INTERRUPT CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
TMR0IE
R/W-0
INT0IE
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
RBIE
Note:
PIC18(L)F2X/4XK22
(1)
(2)
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.
TMR0IF
R/W-0
x = Bit is unknown
INT0IF
R/W-0
DS41412A-page 115
R/W-x
RBIF
bit 0
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