PIC18F24K22-I/SO Microchip Technology, PIC18F24K22-I/SO Datasheet - Page 133

• Manufacturer Part Number: PIC18F24K22-I/SO
• Description: IC PIC MCU 16KB FLASH 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F24K22-I/SO

• Core Size: 8-Bit
• Program Memory Size: 16KB (8K x 16)
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 19x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 64MHz
• No. Of Timers: 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.0
Depending on the device selected and features
enabled, there are up to five ports available. All pins of
the I/O ports are multiplexed with one or more alternate
functions from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has five registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
• LAT register (output latch)
• ANSEL register (analog input control)
• SLRCON register (port slew rate control)
The Data Latch (LAT register) is useful for read-modify-
write operations on the value that the I/O pins are
driving.
A simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in
FIGURE 10-1:
 2010 Microchip Technology Inc.
device)
Note 1:
RD LAT
Data
Bus
WR LAT
or Port
WR TRIS
RD TRIS
RD Port
I/O PORTS
I/O pins have diode protection to V
TRIS Latch
Data Latch
D
D
CK
CK
GENERIC I/O PORT
OPERATION
Q
Q
Q
EN
EN
D
DD
TRISx
and V
Figure
ANSELx
I/O pin
Buffer
Input
SS
.
10-1.
(1)
Preliminary
10.1
PORTA is an 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA. Setting
a TRISA bit (= 1) will make the corresponding PORTA
pin an input (i.e., disable the output driver). Clearing a
TRISA bit (= 0) will make the corresponding PORTA
pin an output (i.e., enable the output driver and put the
contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the PORT latch.
The Data Latch (LATA) register is also memory mapped.
Read-modify-write operations on the LATA register read
and write the latched output value for PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input and one of the comparator outputs to
become the RA4/T0CKI/C1OUT pin. Pins RA6 and
RA7 are multiplexed with the main oscillator pins; they
are enabled as oscillator or I/O pins by the selection of
the main oscillator in the Configuration register (see
Section 24.1 “Configuration Bits”
they are not used as port pins, RA6 and RA7 and their
associated TRIS and LAT bits are read as ‘0’.
The other PORTA pins are multiplexed with analog
inputs, the analog V
comparator voltage reference output. The operation of
pins RA<3:0> and RA5 as analog is selected by setting
the ANSELA<5, 3:0> bits in the ANSELA register which
is the default setting after a Power-on Reset.
Pins RA0 through RA5 may also be used as comparator
inputs or outputs by setting the appropriate bits in the
CM1CON0 and CM2CON0 registers.
The RA4/T0CKI/C1OUT pin is a Schmitt Trigger input.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
The TRISA register controls the drivers of the PORTA
pins, even when they are being used as analog inputs.
The user should ensure the bits in the TRISA register
are maintained set when using them as analog inputs.
EXAMPLE 10-1:
MOVLB
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
Note:
PIC18(L)F2X/4XK22
PORTA Registers
0xF
PORTA
LATA
E0h
ANSELA ; for digital inputs
0CFh
TRISA
On a Power-on Reset, RA5 and RA<3:0>
are configured as analog inputs and read
as ‘0’. RA4 is configured as a digital input.
; Set BSR for banked SFRs
; Initialize PORTA by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure I/O
; Value used to
; initialize data
; direction
; Set RA<3:0> as inputs
; RA<5:4> as outputs
REF
INITIALIZING PORTA
+ and V
REF
DS41412D-page 133
for details). When
- inputs, and the