MCP79410-I/MS Microchip Technology, MCP79410-I/MS Datasheet - Page 8

IC RTC/CALENDER 8MSOP

MCP79410-I/MS

Manufacturer Part Number
MCP79410-I/MS
Description
IC RTC/CALENDER 8MSOP
Manufacturer
Microchip Technology
Type
Clock/Calendar/EEPROMr
Datasheet

Specifications of MCP79410-I/MS

Package / Case
8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
Time Format
HH:MM:SS (12/24 hr)
Date Format
YY-MM-DD-dd
Memory Size
1K (128 x 8)
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Function
Clock/Calendar
Rtc Memory Size
64 B
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Rtc Bus Interface
I2C
Supply Current
400 uA
Clock Format
HH
Clock Ic Type
RTC
Ic Interface Type
I2C
Memory Configuration
128 X 8
Supply Voltage Range
1.8V To 5.5V
Digital Ic Case Style
MSOP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCP79410-I/MS
Manufacturer:
MICROCHI
Quantity:
20 000
MCP7941X
FIGURE 3-2:
3.1.2
A control byte is the first byte received following the
Start condition from the master device
The control byte consists of a control code; for the
MCP7941X this is set as ‘1010111’ for read and write
operations for the EEPROM.
The control byte for accessing the SRAM and RTCC
registers are set to ‘1101111’. The RTCC registers and
the SRAM share the same address space.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’ a read operation is
selected, and when set to a ‘0’ a write operation is
FIGURE 3-3:
DS22266A-page 8
SCL
SDA
DEVICE ADDRESSING AND OPERATION
1
X = Don’t Care
X = Don’t Care
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
1
ACKNOWLEDGE TIMING
ADDRESS SEQUENCE BIT ASSIGNMENTS
1
CONTROL
SRAM RTCC CONTROL BYTE
2
EEPROM CONTROL BYTE
CONTROL
CODE
0
CODE
1
1
3
Data from transmitter
0
0
1
4
1
1
1
(Figure
1
5
1
1
R/W
3-2).
R/W
6
Preliminary
7
{“A7” is “Don’t Care” for normal EEPROM
operations, but is used to access unique ID
location and STATUS register.)
X
X
Acknowledge
selected. The next byte received defines the address of
the data byte
transferred first, followed by the Least Significant bits
(LSb).
Following the Start condition, the MCP7941X monitors
the SDA bus, checking the device type identifier being
transmitted.
‘1101111’ code, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the MCP7941X will select a read
or write operation.
8
Bit
ADDRESS BYTE
ADDRESS BYTE
9
1
(Figure
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Upon
Data from transmitter
2
3-3). The upper address bits are
receiving
 2010 Microchip Technology Inc.
A
0
3
A
0
an
‘1010111’
or

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