AT88RF04C-MVB1G Atmel, AT88RF04C-MVB1G Datasheet - Page 125
AT88RF04C-MVB1G
Manufacturer Part Number
AT88RF04C-MVB1G
Description
CRYPTOMEMORY 1-4KBIT 4ZONE MVB
Manufacturer
Atmel
Series
CryptoMemory®, CryptoRF®r
Datasheets
1.AT97SC3204-X1DB150.pdf
(8 pages)
2.AT88RF04C-MR1G.pdf
(11 pages)
3.AT88RF04C-MVB1G.pdf
(158 pages)
4.AT88RF04C-MVB1G.pdf
(2 pages)
Specifications of AT88RF04C-MVB1G
Rf Type
Read / Write
Frequency
13.56MHz
Features
ISO1444-2, 1444-3, 4-kbits
Package / Case
MVB Module
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- AT97SC3204-X1DB150 PDF datasheet
- AT88RF04C-MR1G PDF datasheet #2
- AT88RF04C-MVB1G PDF datasheet #3
- AT88RF04C-MVB1G PDF datasheet #4
- Current page: 125 of 158
- Download datasheet (892Kb)
Appendix L. Understanding Anti-Tearing
L.1.
L.2.
5276C–RFID–3/09
Anti-tearing is an optional feature that protects a write operation from being corrupted due to PICC power loss during
the write operation. This feature can be enabled as needed by the Host during a transaction, it is not controlled by any
configuration register.
Tearing Explained
A tearing attack on a Smartcard transaction involves quickly removing a card from the reader before a transaction has
been completed. The object of a tearing attack is to remove the card from the reader after the Host application has
granted access to a product, but before the cost of the product has been deducted from the value stored on the card.
Both contact and contactless Smartcard transactions may be attacked in this manner. A tearing attack often results in
corruption of a portion of the data stored in the Smartcard.
Tearing attacks can be prevented from succeeding by careful application software development; if access to a product
is not granted until after a Smartcard value debit has occurred, then the attacker cannot achieve his objective. However
data corruption can occur if any Smartcard transaction is interrupted due to power loss.
CryptoRF Anti-Tearing
CryptoRF is designed with an anti-tearing feature that prevents data corruption in the event a memory write operation is
interrupted. Activating the anti-tearing feature impacts both the transaction time and the memory write endurance of the
PICC, so it should be activated only for critical data write operations.
Figure 40 illustrates how a CryptoRF PICC performs an anti-tearing write. A CryptoRF anti-tearing write is a four step
process. The data is written to a buffer EEPROM memory before being written to the final EEPROM memory location.
The EEPROM Anti-Tearing Flag indicates if an anti-tearing write is in progress, or is completed.
The Anti-Tearing Flag is checked each time the PICC is powered up. If the flag indicates a write was in progress, then
the anti-tearing write will be completed before the PICC is allowed to accept any commands.
The memory address and data are written to a buffer EEPROM in step 1, followed by writing the Anti-Tearing Flag in
Step 2. In step 3 the data in the buffer EEPROM is written to the address sent with the write command (the final
EEPROM memory location). The Anti-Tearing flag is cleared in step 4, and the ACK response is returned to the PCD.
If power is interrupted before step 2 is completed, then the write operation fails; the EEPROM contents are unchanged,
and the Anti-Tearing Flag is not set to indicate an anti-tearing write is in progress. If power is interrupted after step 2 is
complete, then the Anti-Tearing flag is set; when the PICC is next powered up, the anti-tearing write will be completed
as part of the POR process. If power is interrupted during step 3 or 4, the Anti-Tearing Flag will be set and the write will
be completed on the next POR.
AT88SC0808/1616/3216/6416CRF, AT88RF04C
125
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