AS3910-BQFT austriamicrosystems, AS3910-BQFT Datasheet - Page 17

• Manufacturer Part Number: AS3910-BQFT
• Description: IC RFID READER SPI 32-QFN
• Manufacturer: austriamicrosystems

Specifications of AS3910-BQFT

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443A, ISO1443B
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AS3910-BQFTTR

AS3910
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
8.9.1 Serial Peripheral Interface (SPI)
For details about SPI timing refer to
Table 6. Serial Peripheral Interface (4-wire Interface) Signal Lines
8.9.2 SPI Operation MODE Bits
When signal SEN is low, the SPI interface is in reset and SDATAO is in tristate; when it is high, SPI interface is enabled. It is recommended to
keep signal SEN low whenever the SPI interface is not in use. SDATAI is sampled at the falling edge of SCLK. All communication is done in
blocks of 8 bits (bytes). First two bits of first byte transmitted after low to high transition of SEN define SPI operation mode.
possible modes:
Table 7. SPI Operation Patterns <A7-A6>
8.9.3 Writing of Data to Addressable Registers (WRITE Mode)
SDATAI is sampled at the falling edge of SCLK (see
register has been written. Auto incrementing address is supported, which means that if after the address and first data byte some additional data
bytes are sent, they are then written to addresses incremented by 1. In case the command is terminated by putting SEN low before a packet of 8
bits composing one byte is sent, writing of this register is not performed. In case the register on the defined address does not exist or it is a read
only register, no write is performed. Following examples show cases of writing a single byte and writing multiple bytes with auto-incrementing
address.
Figure 5. Writing of a Single Byte (falling edge sampling)
www.austriamicrosystems.com/HF_RFID_Reader/AS3910
COMMAND Mode
SDATAI
WRITE Mode
SCLK
READ Mode
FIFO Read
SEN
FIFO Load
SDATAO
SDATAI
MODE
Name
SCLK
SEN
X
Two leading
Zeros indicate
WRITE Mode
0
M1
0
0
1
1
1
MODE
0
Digital Input with pull down
Digital Output with tristate
M0
0
1
0
0
1
A5
DC / AC Characteristics For Digital Inputs and Outputs (page
Digital Input
Digital Input
MODE Pattern (com. bits)
Signal
SCLK raising
edge data is
transferred from
µC
C5
C5
A5
A5
A4
0
1
C4
C4
A4
A4
A3
0
1
Register Address
Figure
C3
A3
A3
C3
A2
0
1
SCLK
falling edge
Data is sampled
5,
A1
Figure
C2
A2
A2
C2
0
1
A0
Revision 2.3
6). A SEN LOW pulse indicates the end of the WRITE command after
C1
A1
A1
C1
0
1
Signal Level
CMOS
CMOS
CMOS
CMOS
D7
C0
A0
A0
C0
0
1
D6
WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
RD7
RD7
D7
D5
RD6
RD6
D6
SPI Enable
Serial Data input
Serial Data output
Clock for serial communication
D4
8).
RD5
RD5
D5
MODE Related Data
D3
Register Data
RD4
RD4
D4
Data is moved to
D2
Description
RD3
RD3
D3
D1
Address
A5-A0
RD2
RD2
D0
Table 7
D2
SEN falling
edge signals
end of WRITE
Mode
RD1
RD1
defines
D1
X
17 - 47
RD0
RD0
D0