RFPIC12F675HT-I/SS Microchip Technology, RFPIC12F675HT-I/SS Datasheet - Page 71

• Manufacturer Part Number: RFPIC12F675HT-I/SS
• Description: IC MCU 1KX14 RF FSK/ASK 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of RFPIC12F675HT-I/SS

• Frequency: 850MHz ~ 950MHz
• Applications: RKE, Security Systems
• Modulation Or Protocol: ASK, FSK
• Data Rate - Maximum: 40 kbps
• Power - Output: 10dBm
• Current - Transmitting: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 1024 x 14 words Flash, 128 x 8 Byte EEPROM, 64 x 8 Byte SRAM
• Voltage - Supply: 2V ~ 5.5V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 1024 B
• Data Ram Size: 64 B
• Interface Type: USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4 bit
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC124002 - MOD SKT PROMATEII 18SOIC/20SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details
• Other names: RFPIC12F675HT-ISS

FIGURE 10-12:
TABLE 10-9:
10.7
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify. Only the
Least Significant 7 bits of the ID locations are used.
 2003 Microchip Technology Inc.
81h
2007h
Legend: u = Unchanged, shaded cells are not used by the Watchdog Timer.
Address
T0CKI
pin
(= F
CLKOUT
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register.
OSC
T0SE
ID Locations
OPTION_REG GPPU INTEDG
Config. bits
/4)
Name
SUMMARY OF WATCHDOG TIMER REGISTERS
Watchdog
WDTE
Timer
WATCHDOG TIMER BLOCK DIAGRAM
T0CS
Bit 7
CP
0
1
BODEN MCLRE PWRTE WDTE
Bit 6
PSA
0
1
T0CS
Bit 5
Prescaler
8-bit
Preliminary
T0SE
Bit 4
8
PS0 - PS2
Bit 3
PSA
10.8
If
programmed, the on-chip program memory can be
read out for verification purposes.
Note:
the
F0SC2
Bit 2
PS2
Code Protection
code
The entire data EEPROM and FLASH
program memory will be erased when the
code protection is turned off. The INTOSC
calibration data is also erased. See
rfPIC12F675 Programming Specification
for more information.
PSA
PSA
F0SC1
1
0
1
0
Bit 1
PS1
protection
SYNC 2
Cycles
Time-out
F0SC0
rfPIC12F675
WDT
Bit 0
PS0
bit(s)
1111 1111 1111 1111
uuuu uuuu uuuu uuuu
POR, BOD
Value on
Data Bus
have
Set Flag bit T0IF
8
DS70091A-page 69
TMR0
on Overflow
Value on all
not
RESETS
other
been