SI4010-B1-GS Silicon Laboratories Inc, SI4010-B1-GS Datasheet
SI4010-B1-GS
Specifications of SI4010-B1-GS
Related parts for SI4010-B1-GS
SI4010-B1-GS Summary of contents
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... Home automation and security Remote keyless entry LDO REGULATOR DIVIDER PA FSK INTEGRATED 8051 MCU I/O RAM/ NVM INTERFACE ROM 8 Kbyte Copyright © 2010 by Silicon Laboratories Si4010 - RYSTAL LESS O RANSMITTER Si4010 TXP LOOP ANTENNA TXM OOK EEPROM 128-bit Si4010 ...
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... Si4010 2 Rev. 0.5 ...
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... PCB Land Pattern 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8. PCB Land Pattern 14-pin SOIC Package Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10. System Description 10.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2. Setting Basic Si4010 Transmit Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.2.1. Package Type..................................................................................................... 35 10.2.2. Output Power...................................................................................................... 35 10.2.3. Modulation, Encoding, and Data Rate................................................................ 37 10.2.4. Output Frequency............................................................................................... 37 10.2.5. Battery Life Calculation....................................................................................... 38 10 ...
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... Si4010 20. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 21. CIP-51 Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 21.1. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 21.1.1. Instruction and CPU Timing................................................................................62 21.2. CIP-51 Register Descriptions .67 22. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 22.1. Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 22.2. Internal Data Memory 22.3. External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 22.4. General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 22.5. Bit Addressable Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 22.6. Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 22 ...
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... Functionality Limitations While Using IDE Development Environment . . . . . . . . . 155 35.2. Chip Shutdown Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 35.3. LED Driver Usage while Using IDE Debugging Chain . . . . . . . . . . . . . . . . . . . . . . 156 35.4. LED Driver and Application Development Issues . . . . . . . . . . . . . . . . . . . . . . . . . 157 36. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Rev. 0.5 Si4010 5 ...
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... IGURES Figure 1.1. Si4010 Block Diagram ........................................................................... 12 Figure 2.1. Test Block Diagram with 10-pin MSOP ................................................. 13 Figure 3.1. Si4010 Used in a 5-button RKE System with LED Indicator .................. 14 Figure 3.2. Si4010 with an External Crystal in a 4-button RKE System with LED Indicator 14 Figure 6.1. 10-pin MSOP Package .......................................................................... 20 Figure 6 ...
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... Table 8.1. PCB Land Pattern Dimensions ............................................................... 25 Table 9.1. Recommended Operating Conditions ..................................................... 26 Table 9.2. Absolute Maximum Ratings Table 9.3. DC Characteristics .................................................................................. 27 Table 9.4. Si4010 RF Transmitter Characteristics ................................................... 28 Table 9.5. Low Battery Detector Characteristics ...................................................... 31 Table 9.6. Optional Crystal Oscillator Characteristics .............................................. 31 Table 9.7. EEPROM Characteristics ........................................................................ 31 Table 9.8. Low Power Oscillator Characteristics ..................................................... 32 Table 9 ...
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... Si4010 L XREG XREG Definition 11.2. wPA_CAP .......................................................................................... 44 XREG Definition 11.3. bPA_TRIM .......................................................................................... 45 XREG Definition 14.1. bLPOSC_TRIM .................................................................................. 53 XREG Definition 15.1. bXO_CTRL ......................................................................................... 55 XREG Definition 16.3. lFC_COUNT ....................................................................................... 59 XREG Definition 22.1. abMTP_RDATA[16] ........................................................................... 74 8 EGISTERS Rev. 0.5 ...
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... Si4010 L SFR EGISTERS SFR Definition 11.1. PA_LVL ...................................................................................................44 SFR Definition 12.1. ODS_CTRL ............................................................................................. 47 SFR Definition 12.2. ODS_TIMING ..........................................................................................48 SFR Definition 12.3. ODS_DATA ............................................................................................. 49 SFR Definition 12.4. ODS_RATEL ........................................................................................... 49 SFR Definition 12.5. ODS_RATEH ..........................................................................................50 SFR Definition 12.6. ODS_WARM1 ......................................................................................... 50 SFR Definition 12.7. ODS_WARM2 ......................................................................................... 51 SFR Definition 13.1. LC_FSK ...................................................................................................52 SFR Definition 14.2. SYSGEN .................................................................................................54 SFR Definition 16 ...
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... Si4010 SFR Definition 32.1. RTC_CTRL ........................................................................................... 134 SFR Definition 33.1. TMR_CLKSEL ....................................................................................... 143 SFR Definition 33.2. TMR2CTRL ........................................................................................... 144 SFR Definition 33.3. TMR2RL ................................................................................................ 146 SFR Definition 33.4. TMR2RH ...............................................................................................146 SFR Definition 33.5. TMR2L .................................................................................................. 147 SFR Definition 33.6. TMR2H .................................................................................................. 147 SFR Definition 33.7. TMR3CTRL ........................................................................................... 148 SFR Definition 33 ...
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... Like all wireless devices, users are responsible for complying with applicable local regulatory requirements for radio transmissions. The embedded CIP-51 8051 MCU provides the core functionality of the Si4010. User software has com- plete control of all peripherals, and may individually shut down any or all peripherals for power savings. A space on-chip one-time programmable NVM memory is available to store the user program and can also store unique transmit IDs ...
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... AES 128b ACCEL GPIO0/XTAL/VPP C2 GPIO1 GPIO2 GPIO3 GPIO4/C2DAT PORT CONTR GPIO5/C2CLK/LED GPIO6 14P SOIC GPIO7 Package GPIO8 Only GPIO9 Figure 1.1. Si4010 Block Diagram 12 MEMORY RF ANALOG CORE CONTROLLER NVM EEPROM HVRAM 8 KB 128-bit 8 Byte OOK ODS DIVIDER FSK LCOSC LPOSC SFR ...
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... Test Circuit TEST MATCHING EQUIPMENT NETWORK Figure 2.1. Test Block Diagram with 10-pin MSOP 1 10 GPIO0 GPIO1 2 9 GND GPIO2 TXM GPIO3 Si4010- TXP GPIO4 5 6 VDD LED Rev. 0.5 Si4010 GP1 GP2 TESTER GP3 INTERFACE GP4 GP5 13 ...
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... Figure 3.1. Si4010 Used in a 5-button RKE System with LED Indicator 3.2. Si4010 with an External Crystal in a 4-Button RKE System with LED Indicator CR2032 COIN CELL C3 1 LOOP ANTENNA Figure 3.2. Si4010 with an External Crystal in a 4-button RKE System with LED Indicator 14 1 GPI0 GPIO1 2 GND GPIO2 U1 ...
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... Ordering Information Table 4.1. Product Selection Guide Si4010-B1- Si4010-B1- Si4010-C2- Si4010-C2- Notes: 1. Add an “(R)” at the end of the device part number to denote tape and reel option. 2. Assumes LED driver is used and no external crystal. 256 8 128 256 8 128 256 8 128 256 8 128 Y ...
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... GPIO0/XTAL 2 GND 3, 4 TXM, TXP 5 VDD 6 LED GPIO[4: GPIO1 2 9 GPIO2 Si4010- GPIO3 4 7 GPIO4 5 6 LED Description General purpose input pin. Can be configured as an input pin for a crystal. Ground. Connect to ground plane on PCB. Transmitter differential outputs. Power. Dedicated LED driver. ...
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... GND Ground. Connect to ground plane on PCB. 3 TXM Transmitter differential output. 4 TXP Transmitter differential output. 5 VDD Power. 6 C2CLK C2 clock interface. 7 C2DAT C2 data input/output pin GPIO[3:1] General purpose input/output pins GPIO1 2 9 GPIO2 Si4010- GPIO3 4 7 C2DAT/GPIO4 5 6 C2CLK/LED Description Rev. 0.5 Si4010 17 ...
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... TXM, TXP 6 VDD 7,8 GPIO[7:6] 9 LED 10,11,12,13 GPIO[4:1] 14 GPIO8 18 14 GPIO8 2 13 GPIO1 3 12 GPIO2 Si4010- GPIO3 5 10 GPIO4 6 9 LED 7 8 GPIO6 Description General purpose input/output pin General purpose input pin. Can be configured as an input pin for a crystal Ground. Connect to ground plane on PCB ...
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... Description General purpose input/output pin +6.5 V required for NVM (OTP) Memory programming Ground. Connect to ground plane on PCB Transmitter differential outputs Power General purpose input/output pins C2 clock interface C2 data input/output pin General purpose input/output pins General purpose input/output pin Rev. 0.5 Si4010 19 ...
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... Si4010 6. Package Specifications 6.1. 10-Pin MSOP Figure 6.1 illustrates the package details for the Si4010, 10-pin MSOP package. Table 6.1 lists the values for the dimensions shown in the illustration. Figure 6.1. 10-pin MSOP Package Table 6.1. Package Dimensions Symbol Millimeters Min ...
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... SOIC Package Figure 6.2 illustrates the package details for the Si4010, 14-pin SOIC package. Table 6.2 lists the values for the dimensions shown in the illustration. Figure 6.2. 14-pin SOIC Package Table 6.2. Package Dimensions Symbol Min A — A1 0. ...
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... Si4010 7. PCB Land Pattern 10-Pin MSOP Figure 7.1. 10-Pin MSOP Recommended PCB Land Pattern 22 Rev. 0.5 ...
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... The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD- 020 specification for Small Body Components. Rev. 0.5 Si4010 MAX 4.40 REF 0.50 BSC — 0.30 1 ...
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... Si4010 8. PCB Land Pattern 14-pin SOIC Package Figure 8.1. 14-pin SOIC Recommended PCB Land Pattern 24 Rev. 0.5 ...
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... The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD- 020 specification for Small Body Components. Rev. 0.5 Si4010 MAX 5.40 1.27 BSC 0.60 1.55 25 ...
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... Si4010 9. Electrical Characteristics Table 9.1. Recommended Operating Conditions Parameter Symbol Supply Voltage V Supply Voltage Slew Rate Ambient Temperature Digital Input Range *Note: Recommend bypass capacitor = 1 µF; slew rate measured 1 V < V Table 9.2. Absolute Maximum Ratings Parameter Supply Voltage 3 Input Current ...
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... Only sleep timer is enabled All GPIO floating or held high V > 200 mV OUT Trip point at 0. Trip point at 0. TBD SOURCE I = TBD SINK Rev. 0.5 Si4010 Min Typ Max Unit — 14.2 — mA — 11.3 — mA — 19.8 — mA — 14.1 — mA — 700 — nA — ...
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... The frequency step size is limited by the frequency noise. 3. Optimum differential load is equal to 4 V/(11.5mA/2 * 4/PI) = 550 Therefore the antenna load resistance in parallel with the Si4010 differential output resistance should equal 50 4. Total NVM copy time = (NVM copy Boot Time per kB) x (NVM data in kB). ...
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... The frequency step size is limited by the frequency noise. 3. Optimum differential load is equal to 4 V/(11.5mA/2 * 4/PI) = 550 Therefore the antenna load resistance in parallel with the Si4010 differential output resistance should equal 50 4. Total NVM copy time = (NVM copy Boot Time per kB) x (NVM data in kB). ...
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... The frequency step size is limited by the frequency noise. 3. Optimum differential load is equal to 4 V/(11.5mA/2 * 4/PI) = 550 Therefore the antenna load resistance in parallel with the Si4010 differential output resistance should equal 50 4. Total NVM copy time = (NVM copy Boot Time per kB) x (NVM data in kB). ...
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... GPI0 configured as crystal 10 oscillator GPI0 configured as crystal — oscillator GPI0 configured as crystal — oscillator Crystal oscillator only, — motional arm inductance Conditions Min Typ — 1000000 50000 Rev. 0.5 Si4010 Typ Max Unit 2 — % Typ Max Unit — 13 MHz 5 — pF — — ...
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... Si4010 Table 9.8. Low Power Oscillator Characteristics V = 1 –40 to +85 °C unless otherwise specified. Use factory-calibrated settings Parameter Programmable Frequency Programmable divider in Range powers 128 Frequency Accuracy Table 9.9. Sleep Timer Characteristics V = 1 –40 to +85 °C unless otherwise specified. Use factory-calibrated settings. ...
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... V. The Si4010 is awakened from standby mode by a falling edge to ground on any one of the GPIO pins. In addition, the Si4010 has a low-power sleep timer for applications where the device is required to wake up and periodically check for events instead of being wakened by a GPIO falling edge ...
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... Si4010 The Si4010 has three timing sources. The LCOSC is the most accurate timing source native to the chip. Each device is factory trimmed and programmed at Silicon Labs to produce a frequency accuracy of better than ±150 ppm over the temperature range °C and ±250 ppm over the industrial range of –40 to +85 ° ...
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... AN370: Si4010 Software Programming Guide. 10.2.1. Package Type The Si4010 has two package type options: 10-pin MSOP or 14-pin SOIC. The customer should choose the package type they are using to properly model the Si4010 RF behavior. 10.2.2. Output Power ...
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... Si4010 Manual Impedance Entry: Determines if the antenna impedance is calculated to meet a desired output power or if the antenna impedance is entered and the spread sheet calculates the resulting impedance. The current drive is adjusted to meet the power target (if possible). Antenna Real(Z) (Ohms): The antenna resistance at the operating frequency. ...
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... Expected FSK Deviation (kHz): The expected FSK deviation with quantization error 10.2.4. Output Frequency The output frequency does not require the use of the calculator and is set by using the following API com- mands: vFCast_Setup() vFCast_Tune(desired frequency) rate. Rev. 0.5 Si4010 37 ...
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... Si4010 10.2.5. Battery Life Calculation The calculator also estimates battery life of a system given the packet setup and number of button pushes per day. The inputs to the calculator are all of the above inputs plus the following: Packet Setup: Number of bits in Packet—Number of bits in the packet excluding the preamble bits ...
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... Applications Programming Interface (API) Commands The following is a list of API commands for the Si4010. For detailed descriptions of the API commands see the application note AN370: Si4010 Software Programming Guide. AES Module Functions: vAes_Cipher vAes_InvGenKey vAes_InvCipher Button Service Module Functions: vBsr_Setup ...
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... Si4010 Frequency Casting Module Functions: vFCast_Setup vFCast_XoSetup vFCast_Tune vFCast_FineTune vFCast_FskAdj HVRAM Module Functions: vHvram_Write bHvram_Read Multi-Time Programmable Module Functions: lMtp_GetDecCount vMtp_IncCount vMtp_SetDecCount bMtp_Write vMtp_Strobe pbMtp_Read Battery Measurement Module Functions: iMVdd_Measure Non-Volatile Memory Copy Module Functions: vNvm_SetAddr wNvm_GetAddr bNvm_CopyBlock vNvm_McEnableRead vNvm_McDisableRead Output Data Serializer Module Functions: ...
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... System Module Functions: vSys_Setup vSys_BandGapLdo vSys_ForceLc wSys_GetRomId wSys_GetChipId bSys_GetRevId lSys_GetProdId wSys_GetKeilVer vSys_SetClkSys lSys_GetMasterTime vSys_IncMasterTime vSys_SetMasterTime vSys_LedIntensity vSys_LpOscAdj vSys_Shutdown bSys_GetBootStatus vSys_FirstPowerUp vSys_16BitDecLoop vSys_8BitDecLoop Sleep Timer Module Functions: lSleepTim_GetCount vSleepTim_SetCount bSleepTim_CheckDutyCycle vSleepTim_AddTxTimeToCounter lSleepTim_GetOneHourValue Rev. 0.5 Si4010 41 ...
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... Si401X transmitters. With proper filtering and layout techniques, the Si4010 can conform to US FCC part 15.231 and European EN 300 220 regulations. Edge rate control is also included for OOK mode to reduce harmonics that may otherwise violate government regulations ...
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... If either the current or voltage is maximized prior to using the loop, the loop would not be able to further adjust the current or voltage and hence fail to operate properly. Rev. 0.5 Si4010 43 ...
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... Si4010 11.1. Register Description SFR Definition 11.1. PA_LVL Bit 7 6 PA_LVL_NSLICE[4:0] Name Type Reset SFR Address = 0xCE Bit Name PA_LVL_ Number of Slices Enabled in the PA Driver. +-This parameter determines the output current drive of the PA. The values entered 7:3 NSLICE into this register come from the Power Amplifier Module API. ...
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... This parameter boost the bias current of the PA by 1.5 times up to 10.5 mA. The 4 DRV values entered into this register come from the Power Amplifier Module API. This bit should be set without changing the other bits. 3:0 Reserved PA_MAX_ Reserved Reserved DRV R/W 0 Function Rev. 0.5 Si4010 Reserved Reserved 45 ...
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... Si4010 12. Output Data Serializer (ODS) 12.1. Description The ODS block is responsible for synchronizing the output data to the required data rate and maintaining a steady data flow during transmission. The serializer accomplishes the following functions: Controls the edge rate of the PA on/off transitions. ...
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... Force PA On. .0: Normal operation. 1 FORCE_PA 1: Force PA on. In addition, PA_LVL_NSLICE[4:0] in PA_LVL register is passed directly through the serializer, unchanged. Enable the Serializer. 0 ODS_EN 0: Disable the ODS. 1: Enable the ODS FSK_ FORCE_ FORCE_ MODE LC R/W R/W R Function Rev. 0.5 Si4010 FORCE_ ODS_EN DIV PA R/W R/W R ...
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... Si4010 SFR Definition 12.2. ODS_TIMING Bit 7 6 ODS_GROUP_WIDTH[2:0] Name R/W R/W Type 0 0 Reset SFR Address = 0xAA Bit Name Controls Symbol Group width, from 2–8 Symbols. Set transmit 5 symbol groups obtained from 4/5 encoding. Or set send ODS_ 8 symbol group obtained from Manchester encoding of 4 bits. Note that ...
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... R/W R/W Type 0 0 Reset SFR Address = 0xAC Bit Name ODS_RATEL Lower Byte of the 15-bit Wide ODS Data Rate Field. 7:0 [7:0] Symbol rate produced by the serializer is 24MHz/(ods_datarate*(ods_ck_div+1 ODS_DATA[7:0] R Function ODS_RATEL[7:0] R/W R/W R Function Rev. 0.5 Si4010 R/W R/W R ...
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... Si4010 SFR Definition 12.5. ODS_RATEH Bit 7 6 Name Reserved R R/W Type 0 0 Reset SFR Address = 0xAD Bit Name 7 Reserved Read as 0. Write has no effect. ODS_ Upper Bits of 15-bit ODS Data Rate Field. 6:0 RATEH See the ODS_RATEL for description of the serializer data rates. ...
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... ODS_ transmission or on the transition from OOK. Zero bit to OOK One bit. 3:0 WARM_ Interval is in 64*clk_ods cycles resolution LC[3:0] Interval = 64 x ods_warm_pa x (ods_ck_div+1)/24 MHz When clk_ods is in range of 3-8 MHz, warm-up interval range is from µ ODS_WARM_LC[3: Function Rev. 0.5 Si4010 R ...
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... Si4010 13. LC Oscillator (LCOSC) The Si4010 VCO is a fully integrated CMOS LC oscillator that operates at approximately 3.9 GHz. This block in conjunction with a programmable frequency divider generates the transmit carrier frequency. The technology behind the VCO is based on the Silicon Laboratories Si500 crystal-less oscillator chip and forms the core of the Si4010s' crystal-less operation ...
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... XREG Definition 14.1. bLPOSC_TRIM Bit 7 6 Name Type 1 1 Reset XREG Address = 0x4002 Bit Name Low Power Oscillator Trimming. LPOSC_ 7:0 ±16% range with 0.14 % resolution. Setting all the bits to low will maximize the fre- TRIM[7:0] quency of operation LPOSC_TRIM[7:0] R Function Rev. 0.5 Si4010 ...
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... Si4010 SFR Definition 14.2. SYSGEN Bit 7 6 Name SYSGEN_ Re-served PWR_1ST SHUT- DOWN R/W R Type 0 0 Reset SFR Address = 0xBE Bit Name System General Shutdown. Setting this bit causes shutdown of MCU and most analog. Recovery from this is via SYSGEN_ falling edge on any GPIO, which results in a power up and a power on reset. This is ...
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... Note that operation of the XO requires that the bandgap be enabled with the System Module Function API. The input XO_CKGOOD status bit is in the SFR SYSTEM reg- 0 XO_ENA ister. 0: Crystal oscillator disabled. 1: Crystal oscillator enabled Reserved XO_TST[1:0] R Function Rev. 0.5 Si4010 XO_LOW XO_ENA CAP R/W R ...
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... Si4010 16. Frequency Counter The frequency counter allows the measurement of the ratio of two selected clock sources: a low frequency clock which defines a counting interval, and a high frequency clock which is counted. The frequency counter consists of an interval counter, driven by one of the six clock sources. Programming of the interval counter determines how long the main counter will count one of the two high speed clocks, LC oscillator or DIVIDER output ...
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... Note: FC_INTERVAL is not allowed to take on numbers higher than 43. If the number is higher than 43, then the interval counted is forced to 1. The output of the frequency counter is in the XREG FC_COUNT. The user is recommended to use the Fre- quency Counter Module Function API to set the following registers. Rev. 0.5 Si4010 57 ...
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... Si4010 16.1. Register Description SFR Definition 16.1. FC_CTRL Bit 7 6 Name FC_DONE FC_BUSY FC_DIV_ R/W R/W Type 0 0 Reset SFR Address = 0x9B Bit Name Frequency Counter Done. Counting done, interrupt generation level signal. Must be cleared by software ISR also cleared written to fc_busy, which denotes the start of the next count. Any ...
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... Type 0 0 Reset XREG Address = 0x4008 Bit Name Frequency Counter Output. FC_COUNT 22:0 Counter output value. When the counter is running and the value is read then the [22:0] current on the fly value will be read FC_INTERVAL[5:0] R/W 0 Function ... FC_COUNT[22:0] R ... Function Rev. 0.5 Si4010 ...
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... Si4010 17. Sleep Timer The Si4010 includes a very low-power sleep timer that can be used to support the transmit duty cycle requirements of the ETSI specification or self-wakeup for button independent applications. It consist of a low speed (~2.1 kHz), very low power oscillator with a 24 bit down counter. When programmed to its maxi- mum interval it takes ~2 ...
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... Program and Data Memory Security l DATA BUS B REGISTER STACK POINTER TMP1 TMP2 SRAM ADDRESS SRAM ALU REGISTER DATA BUS SFR_ADDRESS BUFFER D8 SFR_CONTROL SFR BUS D8 SFR_WRITE_DATA D8 INTERFACE SFR_READ_DATA MEM_ADDRESS D8 MEM_CONTROL MEMORY MEM_WRITE_DATA A16 INTERFACE MEM_READ_DATA PIPELINE D8 INTERRUPT INTERFACE EMULATION_IRQ D8 D8 REGISTER Rev. 0.5 Si4010 SYSTEM_IRQs 61 ...
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... Si4010 With the CIP-51's maximum system clock at 24 MHz, it has a peak throughput of 24 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions in the function of the required clock cycles. Clocks to Execute 1 Number of Instructions 26 21.1. Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ ...
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... direct byte ORL direct, #data OR immediate to direct byte XRL A, Rn Exclusive-OR Register to A XRL A, direct Exclusive-OR direct byte to A XRL A, @Ri Exclusive-OR indirect RAM to A XRL A, #data Exclusive-OR immediate to A XRL direct, A Exclusive- direct byte Bytes Rev. 0.5 Si4010 Clock Cycles ...
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... Si4010 Table 21.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement Rotate A left RLC A Rotate A left through Carry RR A Rotate A right RRC A Rotate A right through Carry SWAP A Swap nibbles of A Data Transfer ...
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... Compare immediate to Register and jump if not equal CJNE @Ri, #data, rel Compare immediate to indirect and jump if not equal DJNZ Rn, rel Decrement Register and jump if not zero DJNZ direct, rel Decrement direct byte and jump if not zero NOP No operation Bytes Rev. 0.5 Si4010 Clock Cycles ...
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... Si4010 Notes on Registers, Operands and Addressing Modes Register R0–R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00– ...
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... The DPL register is the low byte of the 16-bit DPTR. SFR Definition 21.2. DPH Bit 7 6 Name Type 0 0 Reset SFR Address = 0x83 Bit Name Data Pointer High. 7:0 DPH[7:0] The DPH register is the high byte of the 16-bit DPTR DPL[7:0] R Function DPH[7:0] R Function Rev. 0.5 Si4010 ...
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... Si4010 SFR Definition 21.3. SP Bit 7 6 Name Type 0 0 Reset SFR Address = 0x81 Bit Name Stack Pointer. 7:0 SP[7:0] The Stack Pointer holds the location of the top of the stack. The stack pointer is incre- mented before every PUSH operation. The SP register defaults to 0x07 after reset. ...
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... SFR Definition 21.5. B Bit 7 6 Name Type 0 0 Reset SFR Address = 0xF0; Bit-Addressable Bit Name B Register. 7:0 B[7:0] This register serves as a second accumulator for certain arithmetic operations B[7:0] R Function Rev. 0.5 Si4010 ...
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... Si4010 SFR Definition 21.6. PSW Bit Name R/W R/W Type 0 0 Reset SFR Address = 0xD0; Bit-Addressable Bit Name Carry Flag This bit is set when the last arithmetic operation resulted in a carry (addition bor- row (subtraction cleared to logic 0 by all other arithmetic operations. ...
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... Memory Organization The memory organization of the Si4010 is similar to that of a standard 8051. There are two separate mem- ory spaces: program memory and data memory. Program and data memory share the same address space but are accessed via different instruction types. However, this device is unique since it has the pro- gram and data memory spaces combined into one ...
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... Si4010 22.1. Program Memory Program memory consists of 4.5KB for RAM and 12KB of ROM. The device employs a unified CODE/XDATA RAM memory. On 8051 architecture the external data memory (XDATA) space is physically different from the program memory (CODE); they can be accessed with different instructions. On this device the RAM can store both CODE and XDATA at any location ...
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... NVM memory is only accessible indirectly through Silicon Labs provided API functions for NVM access ini- tialization and read of formatted blocks of data generated by the NVM programmer. Programming of the NVM can be only done by Silicon Labs provided tools not possible to program the NVM by writing to registers. Rev. 0.5 Si4010 73 ...
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... Si4010 22.10. MTP (EEPROM) Memory The MTP memory is a special block not organized as a usual memory. The memory output is mapped to the XDATA address space as a XREG register (abMTP_RDATA[16]) 16 byte read only array at addresses 0x4040 .. 0x404F. Writing to the MTP memory can be done only indirectly by using the Silicon Labs pro- vided API ROM functions ...
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... For debugging purposes user will not program the NVM, but will use the RAM for code development. In that case the device will only contain factory settings and go through much shorter startup routine, which would take less than finish. Rev. 0.5 Si4010 75 ...
Page 76
... Si4010 23.2. Reset Reset circuitry allows the controller to be easily placed in a predefined default condition. There is only one external reset source for the device, which is power on reset. It get invoked at two occasions: 1. Power is supplied to the device. This means connecting the power supply to disconnected device. ...
Page 77
... In such a scenario, this NVM region will not be loaded by boot, but by the user application. That region of NVM is labeled as User App region in Figure 23.1, “NVM Address Map”. Boot routine will not know about the data there. Rev. 0.5 Si4010 77 ...
Page 78
... Si4010 NVM 8KB 0xE000 Set by the factory setup wBoot_NvmUserBeg Optional gap User App (App Use) 0xFFC0 0xFFFF Figure 23.1. NVM Address Map 23.5. Device Boot Process The boot process works in the following sequence: 1. Boot is invoked by cycling power to the internals of the chip (which includes power cycle to the whole chip) or waking up by button press pressing a Reset button in the IDE development platform ...
Page 79
... The visual representation of the RAM is in Figure 23.2. The detailed explanation of the boot control data variables are in Table 23.1 to SFR Definition 23.1. The user code or user development environment need to pay attention to the content of the following vari- ables. All are stored in big endian fashion (MSB at the lower address): Rev. 0.5 Si4010 79 ...
Page 80
... Si4010 wBoot_DpramTrimBeg .. this variable points to the first occupied (by factory data) address of RAM. Therefore, the user development platform needs to read this variable to determine what the available RAM area for user CODE/XDATA is. bBoot_BootStat .. boot status result. User code should check this value at its beginning. If the value is ...
Page 81
... NVM later on. Boot status. User program can read this byte and decide BYTE whether the boot finished correctly. If not, then it can blink LED or not to continue with running the code. See the bBoot_BootStat bit description table. Rev. 0.5 Si4010 81 ...
Page 82
... Si4010 SFR Definition 23.1. BOOT_BOOTSTAT Bit 7 6 BS_GPIO_ RESERVED Name XTAL R R Type 0/1 0 Reset XREG Address = 0x11FF Bit Name GPIO0 Read before Boot. BS_GPIO_ 7 Read GPIO0 value at the very beginning of the boot prior to optionally turning on the XO XTAL (crystal oscillator). 6:5 ...
Page 83
... Used for Factory and User program states, ignored in Run state. When this bit is set 0 RUN_SYS the boot routine will jump to CODE address 0x0000. Forced by the debugging chain if the device is connected to the IDE CODE_ Reserved BOOT_ RUN_ POR POR R/W R/W R Function Rev. 0.5 Si4010 BOOT_ CODE_ FAIL_ DONE_ RUN_SYS SYS SYS R/W R/W R ...
Page 84
... Si4010 23.9. Boot Routine Destination Address Space The boot process reads the formatted data from NVM and writes it to the desired destination. The format supports different address regions based on the destination (write) address. The destination address is part of the NVM content data frame format. ...
Page 85
... These steps can be combined into a single programming step. Step 2. is optional and is convenient when part specific data needs to be added later to the NVM load. Rev. 0.5 Si4010 85 ...
Page 86
... Si4010 23.11. Retest and Retest Configuration When the part is programmed as a Run part, the C2 interface is disabled and nobody can access the part externally. However, Silicon Labs needs to be able to retest the part in case it returns as a failed part from a customer application. Silicon Labs understands that customer may have programmed sensitive informa- tion into the NVM which should not be revealed to anybody, not even to Silicon Labs, during the retest pro- cess ...
Page 87
... This bit is in PROT3_CTRL.NVM_C2_PROT and it corresponds to NVM Disable checkbox on the NVM programmer GUI. Once these options are programmed to the part they cannot be undone or changed. Additional setting of these options after the part is made a Run part is not possible either. Description Rev. 0.5 Si4010 87 ...
Page 88
... Si4010 23.12. Boot and Retest Protection Control Register The boot process monitors the value of an NVM byte called PROT3_CTRL. There is not a corresponding hardware register to this byte value in the Factory region at the beginning of NVM. The register contains Retest protection flags described above and modification of the boot for User part. ...
Page 89
... Run, NVM_BLOWN=3’b11x. In all other cases the value of this bit is PROT ignored. Displays Chip Program Level. NVM_ The bits can only be set to 1, write 0 has no effect: BLOWN 2:0 001 .. Factory [2:0] 011 .. User 111 .. Run MTP_ NVM_ PROT WR_ PROT R R/W R Function Rev. 0.5 Si4010 NVM_BLOWN[2:0] R/W R/W R ...
Page 90
... CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the Si4010. This allows the addi- tion of new functionality while retaining compatibility with the MCS-51™ instruction set. Table 24.2 lists the SFRs implemented in the Si4010 device family ...
Page 91
... P0CON 0x90 Port 1 Latch P1 0xA5 Port 1 Configuration P1CON 0xA0 Port 2 Latch P2 0xCE Power Amplifier Level PA_LVL 0x87 Power Control PCON 0xB5 Port Control PORT_CTRL Description Rev. 0.5 Si4010 Page 128 67 67 101 102 58 59 109 109 130 130 99 100 103 52 47 ...
Page 92
... Si4010 Table 24.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address 0xB7 Port Interrupt Configuration PORT_INTCFG 0xB6 Port Set PORT_SET 0xDA Protection 0 Control PROT0_CTRL 0xD0 Program Status Word PSW 0x99 Read Bit Data ...
Page 93
... Therefore, the LSB byte of the register will be at the address <reg_addr> while the byte directly at the <reg_addr> is the MSB byte and is empty (read as 0x0), since the register itself is only 23 bits wide. Table 24.3 shows a memory map of the XREG registers in the external memory space. Rev. 0.5 Si4010 93 ...
Page 94
... Si4010 Table 24.3. XREG Register Memory Map in External Memory XDATA Address 0x4002 0x4003 ... 0x4007 0x4008 0x4009 0x400a 0x400b 0x400c 0x400d 0x400e ... 0x4011 0x4012 0x4013 ... 0x4015 0x4016 0x4017 0x4018 ... 0x4026 0x4040 ... 0x404f Note: Multiple byte variables, if they are not arrays, are stored in big endian .. ...
Page 95
... They are aligned towards MSB byte of the wPA_CAP, the one at lower address since the byte ordering is in big endian fashion. Table 24.4. XREG Registers Description PA Variable Capacitor PA MAX Drive bit Low Power Oscillator Trim MTP_Read Data Bytes XO Control Frequency Counter Output Rev. 0.5 Si4010 Page ...
Page 96
... Si4010 25. Interrupts The Si4010 device includes an extended interrupt system supporting a total of 12 interrupt sources with two priority levels. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt condition, the associated interrupt- pending flag is set to logic ‘ ...
Page 97
... CPU is performing an RETI instruction followed by a DIV as the next instruction, and a cache miss event also occurs. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction. Rev. 0.5 Si4010 97 ...
Page 98
... Si4010 Interrupt Source Interrupt Vector Reset 0x0000 External INT 0 (INT0) 0x0003 Timer 2 Overflow 0x000B RESERVED 0x0013 Real Time Clock Tick 0x001B ODS Ready for Data 0x0023 Timer 3 Overflow 0x002B External INT1 0x0033 Reserved 0x003B Reserved 0x0043 Frequency Counter 0x004B Count Done ...
Page 99
... Enable interrupt requests generated by the TF2 flag. Enable External Edge Interrupt 0. This bit sets the masking of External Interrupt 0. 0 EINT0 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the INT0 input EODS ERTC Reserved R/W R/W R Function Rev. 0.5 Si4010 ETMR2 EINT0 R/W R/W R ...
Page 100
... Si4010 SFR Definition 25.2. IP Bit 7 6 Name Reserved PINT1 PTMR3 R/W R/W Type 1 0 Reset SFR Address = 0xB8; Bit-Addressable Bit Name 7 Reserved Read = 1, Write = Don't Care. External Edge Interrupt 1 Priority Control. This bit sets the priority of the External Interrupt 1 interrupt. 6 PINT1 0: External Interrupt 1 set to low priority level ...
Page 101
... Enable Frequency Counter Interrupt. This bit sets the Frequency Counter interrupt. 2 EFC 0: Disable Frequency Counter interrupt. 1: Enable interrupt requests generated by Frequency Counter. 1:0 Reserved Reset value 0x0 must not be changed EVOID1 EVOID0 EFC R R/W R/W R Function Rev. 0.5 Si4010 1 0 Reserved Reserved 101 ...
Page 102
... Si4010 SFR Definition 25.4. EIP1 Bit 7 6 Reserved Name R Type 0 Reset SFR Address = 0xF6 Bit Name 7:5 Reserved Read as 0x0. Write has no effect. VOID1 Interrupt Priority Control. This bit sets the priority of the VOID1 interrupt. 4 PVOID1 0: VOID1 interrupt set to low priority level. ...
Page 103
... Set by Selected GPIO Input by a Selected Edge. INT0_ 0 It gets set irrespective of the EINT0 setting. It must be cleared by software. Hard- FLAG ware will not clear this bit VOID1_ VOID0_ ODS_ FLAG FLAG FLAG R R/W R/W R Function Rev. 0.5 Si4010 INT1_ INT0_ FLAG FLAG R/W R 103 ...
Page 104
... Si4010 25.5. External Interrupts The INT0 and INT1 external interrupt sources are configurable as active high or low. They are edge sensi- tive only, not level sensitive. These are not the same INT0 and INT1 as found on original 8051 architecture. Each of the INT0 and INT1 can invoke interrupt on the rising edge, falling edge, or both edges of the selected GPIO pins associated with the INT0 and INT1, respectively ...
Page 105
... These bits select which Port pin is assigned to INT0. 000: Select GPIO0 001: Select GPIO1 SEL_ 010: Select GPIO2 2:0 INT0[2:0] 011: Select GPIO3 100: Select GPIO4 101: Select GPIO8 110: Select GPIO6 111: Select GPIO7 NEG_ INT0 R/W R Function Rev. 0.5 Si4010 SEL_INT0[2:0] R 105 ...
Page 106
... Si4010 26. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is halted, all interrupts and timers are inactive. The system clock is still running when the CPU is in Stop mode ...
Page 107
... Setting this bit will place the CIP-51 in Idle mode. This bit will always be read IDLE 1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial Ports, and Analog Peripherals are still active GF[5:0] R Function Rev. 0.5 Si4010 STOP IDLE R/W R 107 ...
Page 108
... Si4010 27. AES Hardware Accelerator The device implements the AES (Advanced Encryption Standard) hardware accelerator not a full hardware solution. The hardware accelerator is used by the Silicon Labs API firmware to implement AES 128 bit encrypt/decrypt functions. If the user wants to implement proprietary AES implementation in firm- ware it is possible to use the AES hardware accelerator ...
Page 109
... SFR Address = 0x85 Bit Name GFM Multiplier Constant Register. GFM_CONST 7:0 This is the constant by which the GFM_DATA is multiplied by. It has to be written [7:0] prior to GFM_DATA GFM_DATA[7:0] R/W R/W R/W R Function GFM_CONST[7:0] R/W R/W R/W R Function Rev. 0.5 Si4010 R/W R R/W R 109 ...
Page 110
... Si4010 SFR Definition 27.3. SBOX_DATA Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Address = 0x86 Bit Name AES SBox Processing. Writing of a value here registers the data for processing. Processed data is regis- SBOX_DATA 7:0 tered into the same register with single CLK_SYS cycle delay. Read from this reg- [7:0] ister reads the processed data ...
Page 111
... There is no software reset other than what a running program can invoke by software means. The only thing the running program can put the device into the shutdown mode, effectively disconnecting power to internal systems of the device. User can wake the device up by connecting any of the GPIO ports to ground. Rev. 0.5 Si4010 111 ...
Page 112
... Si4010 29. Port Input/Output Digital resources are available through I/O pins. The number of I/O depends on the package: 10 pin package .. 6 port pins organized as 6 bottom bits of Port 0. 14 pin package .. 10 port pins organized as a full 8-bit Port 0 and 2 bottom bits of Port 1. ...
Page 113
... The option for Matrix and Roff modes is available only on GPIO[3:1]. Table 29.1. 10–Pin Mode Package Pin Package Pin Number Name 1 GPIO0/XO 10 GPIO1 9 GPIO2 8 GPIO3 7 GPIO4 6 GPIO5/LED Table 29.2. 14–Pin Mode Package Pin Package Pin Number Name 2 GPIO0/XO 13 GPIO1 12 GPIO2 11 GPIO3 10 GPIO4 9 GPIO5/LED 8 GPIO6 7 GPIO7 14 GPIO8 1 GPIO9 Rev. 0.5 Si4010 113 ...
Page 114
... Si4010 Digital logic Wr: PORT_MATRIX Wr: PORT_ROFF PORT_STROBE Rd: PORT_MATRIX Rd: PORT_ROFF gpio_in[n] gpio_push_pull[n] port_push_pull[n] port_oe[n] gpio_dataout[n] port_dataout[n] Figure 29.2. GPIO[3:1] Functional Diagram Functional diagram of the other GPIO ports is in Figure 29. the general GPIO circuit that can be forced by digital control to have limited functionality (e.g., as input only, etc.). ...
Page 115
... LED has to be isolated from the pin as shown in Figure 34.1 and Figure 34.2. The LED is disabled during debugging. C2 FOB 1 button button button 2 button C2DAT button 3 C2CLK LED 4 button button button button Rev. 0.5 Si4010 Can Drive Pullup Roff Low During Option Sleep 115 ...
Page 116
... Si4010 29.2. Pullup Roff Option There is an option to disable the weak pullup pad resistors. This feature is called Roff option. The Roff option is controlled directly by the GPIO pads and persist when the chip is in the shutdown mode. Control of the Roff control bit in the GPIO is described in section 29.4. Pullup Roff and Matrix Mode Option Con- trol ...
Page 117
... Wr: PORT_MATRIX PORT_STROBE E Figure 29.4. Push Button Organization in Matrix Mode GPIO[9] GPIO[8] GPIO[7] GPIO[6] GPIO[0] GPIO[4] GPIO[3] GPIO[2] GPIO[1] Rev. 0.5 Si4010 14 pin package only Pushbuttons connecting the crossing wires: = 117 ...
Page 118
... Si4010 29.4. Pullup Roff and Matrix Mode Option Control Both Roff and Matrix mode options are controlled by the GPIO pad itself. The control is implemented as 2 bit latch inside of the GPIO pads. Both options stay in their used defined states during chip shutdown. In other words, if the chip is in shutdown mode, the digital logic does not have power, but the two GPIO latches keep the user set values of those options ...
Page 119
... The lower the priority number, the higher the functional priority. For example, if the functional- ity with priority 1 is programmed, then controls selecting functionality of priority 2 and above will be ignored no matter what the control settings are. ; Set Matrix mode and keep resistors ; Strobe new Matrix/Roff modes to GPIO Rev. 0.5 Si4010 119 ...
Page 120
... Si4010 Table 29.4. GPIO Special Roles Control and Order GPIO Roles Order 0 VPP XO_CTRL.XP_ENA GPIO 3 P0.0 fixed as input only 1 GPIO 1 P0.1 P0CON.1 Matrix Ind* PORT_CTRL 2 GPIO 1 P0.2 P0CON.2 Matrix, Roff Ind* PORT_CTRL 3 Reference 1 PORT_SET.PORT_REFEN clk_ref GPIO 2 P0.3 P0CON.3 Matrix, Roff Ind* PORT_CTRL ...
Page 121
... The user then can hit the Connect button on the IDE to connect to the chip again. For the IDE to be able to connect to the chip the LED must not be driven (not lit). VDD 50k PORT_CTRL Figure 29.5. GPIO[5] LED Driver Block Diagram VDD GPIO[5]/LED Debug LED disable 2 P0 Rev. 0.5 Si4010 121 ...
Page 122
... Si4010 SFR Definition 29.1. P0 Bit 7 6 Name R/W R/W Type 1 1 Reset SFR Address = 0x80 Bit Name Port 0 Register, GPIO[7:0], Bit Addressable. Write appears at the GPIO[7:0] outputs, read reads directly the GPIO input values. Write output low value 1 .. output open-drain or high drive value in push-pull mode Read: 0 ...
Page 123
... Write appears at the GPIO[15:8] outputs, read reads directly the GPIO input values. 7:0 P1[7:0] Same as for P0. Only GPIO[9:8] are used, write to the rest of the register has no effect, read returns 0 at those bits P0CON[7:0] R/W R/W R Function P1[7:0] R/W R/W R Function Rev. 0.5 Si4010 R/W R/W R R/W R/W R 123 ...
Page 124
... Si4010 SFR Definition 29.4. P1CON Bit 7 6 Name R/W R/W Type 0 0 Reset SFR Address = 0xA5 Bit Name POrt 1 Register GPIO[15:8], Bit Addressable. This bit controls configuration of each corresponding output bit in P1 open-drain, pull up resistor connected (see PORT_ROFF) 7:0 P1CON[7: push-pull, pull up resistor disabled If the pin to be input, it must be configured as open-drain and 1 has to be written as output value to it ...
Page 125
... The actual turning of the LED on and off is controlled by the GPIO[5] output bit in P0. PORT_LED 1:0 [1:0] 00: LED off 01: LED current = 0.62*600uA 10: LED current = 1.00*600uA 11: LED current = 1.62*600uA PORT_ PORT_5_ PORT_ DRV2X MID- RANGE RANGE R/W R/W R/W — Function Rev. 0.5 Si4010 PORT_LED[1:0] MID- R/W R/W R 125 ...
Page 126
... Si4010 SFR Definition 29.7. PORT_SET Bit 7 6 EDGE_ EDGE_ PORT_CLKOUT[1:0] Name INT1 INT0 R/W R/W Type 0 0 Reset SFR Address = 0xB6 Bit Name Edge Control for INT1. EDGE_ This bit controls whether single edge or both edges invoke the interrupt. 7 INT1 0 .. single edge, polarity specified by NEG_INT1 in PORT_INTCFG 1 ...
Page 127
... CLKOUT_DIV recommended to fix all the settings before enabling the output clock generator. The master enable is PORT_CLKEN bit in the PORT_SET register. CLKOUT_SET Enable Clear Divide by 24MHz CLKOUT_DIV[4:0] Figure 30.1. Output Clock Generator Block Diagram Symmetry 1:1 Duty Cycle PORT_SET Rev. 0.5 Si4010 GPIO[6] GPIO[4] 127 ...
Page 128
... Si4010 30.1. Register Description SFR Definition 30.1. CLKOUT_SET Bit 7 6 Name CLKOUT_ CLKOUT_ CLKOUT_ CLR INV R/W R/W Type 0 0 Reset SFR Address = 0x8F Bit Name CLKOUT Clear. Write 1 to this bit clears the generated clock divider. The generated clock output is forced to 0 ...
Page 129
... To monitor when the output gets idle monitor the CLKOUT_CLR bit below. The CLKOUT_DIV bit can be changed any time. The new setting will take effect only after the current period finishes. For the new setting to take effect immediately see CLKOUT_CLR. Function Rev. 0.5 Si4010 129 ...
Page 130
... Si4010 31. Control and System Setting Registers The following are general system setting control registers as well as general purpose scratch pad regis- ters. GPR_CTRL and GPR_DATA can be used as a general purpose 2 byte SFR register. They do not con- trol any hardware on the device. SFR Definition 31.1. GPR_CTRL ...
Page 131
... Output of phase detection PA comparator. When PA is enabled, runs at full 0 PA_COMPOUT clock rate, and is asynchronous to clk_sys. Should be demetastabilized suf- ficiently by transferring to another register for purposes of getting to CPU XO_ ODS_ ODS_NOD CKGOOD EMPTY ATA Function Rev. 0.5 Si4010 TRNG_ PA_ OUT COMPOUT 131 ...
Page 132
... Si4010 32. Real Time Clock Timer The Si4010 device contains a real time clock (RTC) timer. This dedicated timer provides accurate interrupt request pulses in precise time intervals. The device does not contain any hardware nor any battery backed up real time clock. The purpose of RTC timer is to provide accurate time intervals for user application at run time, not an absolute real calendar time ...
Page 133
... TMR2 and TMR3, so there is a need to have separate control over the rtc_tick generator clearing. To get the RTC tick generator running the RTC_ENA=1 must be set. Therefore, even if the RTC interrupt is not used, the RTC timer must be enabled if the user wants to use the rtc_tick as a clock source for TMR2 or TMR3. Rev. 0.5 Si4010 133 ...
Page 134
... Si4010 SFR Definition 32.1. RTC_CTRL Bit 7 6 Name RTC_INT RTC_ENA RTC_CLR Reserved R/W R/W Type 0 0 Reset SFR Address = 0x9C Bit Name Real Time Clock Interrupt Flag. 7 RTC_INT Set after the time interval set by RTC_DIV field elapses. Software must clear the flag. ...
Page 135
... Timers 2 and 3 The Si4010 device includes two identical timers, Timer 2 (TMR2) and Timer 3 (TMR3). Since the timers are identical, the description will refer to Timer 2 (TMR2). The reader can replace the TMR2 with TMR3 in the text to get the description of Timer 3 (TMR3). The description refers to a “Timer” alias for either TMR2 or TMR3 ...
Page 136
... Si4010 33.1. Interrupt Flag Generation Timer 2 has a single interrupt signal going to interrupt controller. Internally, there are 2 interrupt flags, TMR2INTH for high half of the timer and TMR2INTL for low half of the timer, which are combined to gener- ate the final interrupt signal. The low half has a local interrupt flag enable TMR2INTL_EN control bit. ...
Page 137
... Also note that if the capture timer is stopped (TMR2L_RUN=0) the capture event still captures the current counter registers (TMR2H:TMR2L) into the timer reload registers (TMR2H:TMR2RL) and sets the flag TMR2INTH. TMR2L overflow TMR2L TMR2H TMR2RL TMR2RH Reload Rev. 0.5 Si4010 Interrupt TMR2INTH TMR2INTL TMR2INTL_EN TMR2SPLIT TMR2H_CAP TMR2L_CAP TMR2H_RUN TMR2L_RUN ...
Page 138
... Si4010 TMR_CLKSEL 2 TMR2L_RUN clk_sys 0 clk_sys/12 1 rtc_tick (5.33us) 2 rtc_pulse (100us) 3 Capture INT0 INT1 for TMR3 Figure 33.3. Capture 16-bit Mode Block Diagram (Wide Mode) 33.4. 8-bit Timer/Timer Mode (Split Mode) When TMR2SPLIT=1, the timer operates as two independent 8-bit timers. Each of the 8-bit timers can independently operate in either 8-bit timer or 8-bit capture modes ...
Page 139
... TMR2L into the reload register TMR2RL and sets the flag TRM2INTL. Same indepen- dently applies to the upper half TMR2H with its respective registers and flags. TMR2INTH TMR2H TMR2INTL TMR2INTL_EN TMR2SPLIT TMR2H_CAP TMR2RH TMR2L_CAP Reload TMR2H_RUN TMR2L_RUN TMR2L TMR2RL Reload Rev. 0.5 Si4010 Interrupt 139 ...
Page 140
... Si4010 TMR_CLKSEL 2 TMR2H_RUN clk_sys 0 clk_sys/12 1 rtc_tick (5.33us) 2 rtc_pulse (100us TMR2L_RUN INT0 INT1 for TMR3 Figure 33.5. Two 8-bit Timers in Capture/Capture Configuration (Split Mode) 33.6. 8-bit Timer/Capture Mode (Split Mode) When TMR2SPLIT=1, TMR2L_CAP=1 and TMR2H_CAP=0, the split timers operate one in 8-bit timer mode and the other in 8-bit capture mode ...
Page 141
... TMR_CLKSEL 2 TMR2H_RUN clk_sys 0 clk_sys/12 1 rtc_tick (5.33us) 2 rtc_pulse (100us TMR2L_RUN INT0 INT1 for TMR3 Figure 33.6. Two 8-bit TImers in Timer/Capture Configuration (Split Mode) TMR2H TMR2INTH TMR2INTL TMR2INTL_EN TMR2SPLIT TMR2H_CAP TMR2RH TMR2L_CAP Reload TMR2H_RUN TMR2L_RUN TMR2L Capture TMR2RL Rev. 0.5 Si4010 Interrupt 141 ...
Page 142
... Si4010 TMR_CLKSEL 2 TMR2H_RUN clk_sys 0 clk_sys/12 1 rtc_tick (5.33us) 2 rtc_pulse (100us TMR2L_RUN INT0 INT1 for TMR3 Figure 33.7. Two 8-bit Timers In Capture/Timer Configuration (Split Mode) 142 TMR2INTH TMR2H TMR2INTL TMR2INTL_EN TMR2SPLIT TMR2H_CAP Capture TMR2RH TMR2L_CAP TMR2H_RUN TMR2L_RUN TMR2L TMR2RL Reload Rev. 0.5 Interrupt ...
Page 143
... Timer 2 Low Byte Mode Select. Timer 2 low half in split mode or full timer in full mode clock selection. Clock selection encoding is the same for all 4 halves. TMR2L_ 1:0 00: CLK_SYS MODE 01: CLK_SYS/12 10: RTC_TICK = 5.33 µs 11: RTC_PULSE = 100 µ TMR3L_MODE TMR2H_MODE R/W R Function Rev. 0.5 Si4010 TMR2L_MODE R 143 ...
Page 144
... Si4010 SFR Definition 33.2. TMR2CTRL Bit 7 6 TMR2 TMR2 Name INTH INTL INTL_EN R/W R/W Type 0 0 Reset SFR Address = 0xC8; Bit-Addressable Bit Name Timer 2 High Byte Interrupt Flag. TMR2 Interrupt flag for timer high half in split configuration or overall 16 bit timer in wide ...
Page 145
... Timer 2 High Byte Run Model. TMR2H_ 1 TMR2H high byte enable in split configuration, whole timer enable in wide configura- RUN tion. Timer 2 Low Byte Run Model. TMR2L_ 0 TMR2L low byte enable in split configuration, whole timer enable in wide configura- RUN tion. Function Rev. 0.5 Si4010 145 ...
Page 146
... Si4010 SFR Definition 33.3. TMR2RL Bit 7 6 Name Type 0 0 Reset SFR Address = 0xCA Bit Name Timer 2 Capture/Reload Register Low Byte. TMR2RL holds the low byte of the capture/reload value for Timer 2. LSB Byte. Two halves are not double buffered. Write to each of the halves takes effect immedi- ...
Page 147
... SFR Address = 0xCD Bit Name Timer 2 High Byte Actual Timer Value. 7:0 TMR2H[7:0] In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer bit mode, TMR2H contains the 8-bit high byte timer value TMR2L[7:0] R Function TMR2H[7:0] R Function Rev. 0.5 Si4010 147 ...
Page 148
... Si4010 SFR Definition 33.7. TMR3CTRL Bit 7 6 TMR3 TMR3 Name INTH INTL INTL_EN R/W R/W Type 0 0 Reset SFR Address = 0xB9 ; Bit Name Timer 3 High Byte Interrupt Flag. TMR3 Interrupt flag for timer high half in split configuration or overall 16 bit timer in wide ...
Page 149
... Timer 3 High Byte Run Model. TMR3H_ 1 TMR3H high byte enable in split configuration, whole timer enable in wide configura- RUN tion. Timer 3 Low Byte Run Model. TMR3L_ 0 TMR3L low byte enable in split configuration, whole timer enable in wide configura- RUN tion. Function Rev. 0.5 Si4010 149 ...
Page 150
... Si4010 SFR Definition 33.8. TMR3RL Bit 7 6 Name Type 0 0 Reset SFR Address = 0xBA Bit Name Timer 3 Capture/Reload Register Low Byte. TMR3RL holds the low byte of the capture/reload value for Timer 3. LSB Byte. Two halves are not double buffered. Write to each of the halves takes effect immedi- ...
Page 151
... SFR Address = 0xBD Bit Name Timer 3 High Byte Actual Timer Value. 7:0 TMR3H[7:0] In 16-bit mode, the TMR3H register contains the high byte of the 16-bit Timer bit mode, TMR3H contains the 8-bit high byte timer value TMR3L[7:0] R Function TMR3H[7:0] R Function Rev. 0.5 Si4010 151 ...
Page 152
... Si4010 34. C2 Interface The devices include an on-chip Silicon Laboratories 2-Wire (C2) debug interface in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal (C2CLK) and a bi- directional C2 data signal (C2DAT) to transfer information between the device and a host system. The C2 interface is intended to be used by the Silicon Labs or third party development tools ...
Page 153
... Instead of the USB debug adapter the user can also use Silicon Labs ToolStick development tool. The ToolStick has a PCB edge 14 pin connector. Connection in between the device and the ToolStick for soft- ware development and debugging is in Figure 34.2. Rev. 0.5 Si4010 153 ...
Page 154
... Si4010 If pushbutton on keyfob development board, then it has to be isolated by R5 For debugging chain to work, LED must be isolated by R6 VBUS (+5V) Can be used to generate local VDD 1k R2 Figure 34.2. 14-pin C2 ToolStick Connection to Device 154 VDD SW_GPIO4 R5 GPIO4 C2DAT 1k5 VDD LED R6 470 GPIO5 ...
Page 155
... RAM content with the user code will get erased. 2. The LED driver cannot be used when the device is connected to the debug adapters (USB debug adapter or a ToolStick). 3. Once the part is finalized, programmed as Run part, no further debugging is possible. Rev. 0.5 Si4010 155 ...
Page 156
... Si4010 35.2. Chip Shutdown Limitation While developing firmware on an unprogrammed chip the user cannot call the API function vSys_Shutdown() to shutdown the chip without loosing the RAM code downloaded by IDE. Instead, the user should comment out the call to the shutdown function and replace it with a temporary code, which monitors a button press, actually monitoring P0 and P1 port inputs based on the user current port settings ...
Page 157
... GPIO[4] during applicaiton development when the part is in the Factory or User state. There is no issue if the part is in the Run state. See the Errata for possible problem description and the API documentation for possible impact of the application development and available solutions. Rev. 0.5 Si4010 157 ...
Page 158
... AN370: Si4010 Software Programming Guide AN511: Si4010 NVM Burner user's guide AN515: Si4010 Key fob Development Kit Quick-Start Guide AN518: Si4010 Memory Overlay Technique AN526: Si4010 ROM 02.00 API Additional Library Description 158 Rev. 0.5 ...
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... Updated section 2. Ordering Information to reflect the revision B and C silicon Updated table 7.3 DC Characteristics to reflect revision B and C silicon Updated table 7.4 Si4010 RF Transmitter Characteristics to reflect revision B and C silicon Fixed block diagram in figure 8.1. Test Block Diagram with 10-pin MSOP Package Updated section 10. System Description text for ...
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... Si4010 C I ONTACT NFORMATION Silicon Laboratories Inc. Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice ...