SI4430-A0-FM Silicon Laboratories Inc, SI4430-A0-FM Datasheet
SI4430-A0-FM
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SI4430-A0-FM Summary of contents
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... The Si4430 offers advanced radio features including continuous frequency coverage from 900–960 MHz The Si4430’s high level of integration offers reduced BOM cost while simplifying the overall system design. The extremely low receive sensitivity (– ...
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... Si4430 Functional Block Diagram VDD_RF RF LDO VCO LDO TX PA AGC Control RFp RFn LNA Mixers IF LDO BIAS VR_IF 2 PLL LDO VCO LPF CP N Delta Sigma Modulator ANTDIV TXRXSW SPI, & Controller PA_RAMP PWR_CTRL Digital Modem ADC PGA Preliminary Rev. 0.4 RC 32K OSC ...
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... RX and TX FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.2. Packet Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 6.3. Packet Handler TX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 6.4. Packet Handler RX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 6.5. Data Whitening, Manchester Encoding, and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.6. Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.7. Preamble Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.8. Invalid Preamble Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.9. TX Retransmission and Auto Modem Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Preliminary Rev. 0.4 Si4430 Page 3 ...
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... RSSI and Clear Channel Assessment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 10. Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11. Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.1. Crystal Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.2. Layout Practice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 12. Reference Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.1. Complete Register Table and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 13. Pin Descriptions: Si4430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 14. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 15. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 4 Preliminary Rev. 0.4 ...
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... IGURES Figure 1. Si4430 RX/TX Direct-Tie Application Example .......................................................... 16 Figure 2. SPI Timing.................................................................................................................. 18 Figure 3. SPI Timing—READ Mode ..........................................................................................19 Figure 4. SPI Timing—Burst Write Mode .................................................................................. 19 Figure 5. SPI Timing—Burst Read Mode .................................................................................. 19 Figure 6. State Machine Diagram.............................................................................................. 20 Figure 7. TX Timing................................................................................................................... 24 Figure 8. RX Timing .................................................................................................................. 25 Figure 9. Frequency Deviation .................................................................................................. 28 Figure 10. Sensitivity at 1% PER vs. Carrier Frequency Offset ................................................29 Figure 11 ...
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... Si4430 ABLES Table 1. DC Characteristics .......................................................................................................7 Table 2. Synthesizer AC Electrical Characteristics Table 3. Receiver AC Electrical Characteristics Table 4. Transmitter AC Electrical Characteristics Table 5. Auxiliary Block Specifications Table 6. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) ................................... 12 Table 7. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2) .............................................. 12 Table 8. Absolute Maximum Ratings ........................................................................................ 13 Table 9 ...
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... Crystal Oscillator and all other blocks OFF Crystal Oscillator and Main Digital Regulator ON, all other blocks OFF. Crystal Oscillator buffer disabled Synthesizer and regulators enabled txpow[2: (+13 dBm), VDD = 3.3 V txpow[2: (+1 dBm), VDD = 3.3 V Preliminary Rev. 0.4 Si4430 — Min Typ Units 1.8 3.0 — ...
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... Si4430 Table 2. Synthesizer AC Electrical Characteristics Parameter Symbol Synthesizer Frequency F SYNTH Range Synthesizer Frequency F RES 2 Resolution Reference Frequency f REF Reference Frequency f REF_LV 2 Input Level 2 Synthesizer Settling Time t LOCK 2 F Residual FM RMS 2 Phase Noise L(f M Notes: 1. All specification guaranteed by production test unless otherwise noted. ...
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... GFSK with BT = 0.5, channel spacing = 150 kHz Desired Ref Signal 3 dB above sensitivity. Interferer and desired modulated with 40 kbps kHz GFSK with BT = 0.5 IF=937 kHz Measured at RX pins (LO feed through) Preliminary Rev. 0.4 Si4430 Min Typ Max Units 900 — 960 MHz — ...
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... Si4430 Table 4. Transmitter AC Electrical Characteristics Parameter Symbol TX Frequency F SYNTH 1 Range 2 FSK Modulation Data Rate DR FSK OOK Modulation Data DR OOK 2 Rate 1 Modulation Deviation Δf Modulation Deviation Δf RES Resolution 1 Output Power Range Output Steps RF_OUT Output Level RF_V 2 Variation vs. Voltage 2 ...
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... When calibrated using temp A sensor offset register S RES CT Configurable to 30 MHz, 15 MHz, 10 MHz, 4 MHz, 3 MHz, 2 MHz, 1 MHz, or 32.768 kHz ENB RES CT RES RES RES Preliminary Rev. 0.4 Si4430 Min Typ Max Units — 0.5 — °C — 5 — mV/°C — 50 — mV — ...
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... Si4430 Table 6. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) Parameter Symbol Rise Time T Fall Time T Input Capacitance Logic High Level Input Voltage Logic Low Level Input Voltage Input Current Logic High Level Output Voltage Logic Low Level Output Voltage Note: All specification guaranteed by production test unless otherwise noted. ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Caution: ESD sensitive device. Power Amplifier may be damaged if switched on without proper load or termination connected. Parameter A Preliminary Rev. 0.4 Si4430 Value Unit –0.3, +3.6 V –0.3, +8.0 V – ...
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... External reference signal (XOUT) = 0.7 to 1.6 V Production test schematic (unless noted otherwise) All RF input and output levels referred to the pins of the Si4430 (not the RF module) Test Notes: All electrical parameters with Min/Max values are guaranteed by one (or more) of the following test methods. ...
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... Functional Description The Si4430 is a 100% CMOS ISM wireless transceiver with continuous frequency tuning over the complete 900–960 MHz band. The wide operating voltage range of 1.8–3.6 V and low current consumption makes the Si4430 and ideal solution for applications. The Si4430 operates as a time division duplexing (TDD) transceiver where the device alternately transmits and receives data packets ...
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... Si4430 supply voltage C6 C7 100p 100n Figure 1. Si4430 RX/TX Direct-Tie Application Example 30MHz 1u L1 VDD_RF RFp Si4430 3 13 RXn 4 12 VR_IF 5 C10 1u L4 Programmable load capacitors for X1 are integrated. R1, L1-L5 and C1-C4 values depend on frequency band, antenna impedance, output power and supply voltage range. ...
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... Depending upon the system communication protocol, the optimal trade-off between the radio wake time and power consumption can be achieved. Table 9 summarizes the modes of operation of the Si4430. In general, any given mode of operation may be classified as an Active mode or a Power Saving mode. The table indicates which block(s) are enabled (active) in each corresponding mode. With the exception the Shutdown mode, all can be dynamically selected by sending the appropriate commands over the SPI in order to optimize the average current consumption. An “ ...
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... Select high period SW To read back data from the Si4430, the R/W bit must be set to 0 followed by the 7-bit address of the register from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored when R The next eight negative edge transitions of the SCLK signal will clock out the contents of the selected register. The data read from the selected register will be available on the SDO output pin ...
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... ADDR and read from/write to the next address. An SPI burst write transaction is demonstrated in Figure 4 and burst read in Figure 3. As long as nSEL is held low, input data will be latched into the Si4430 every eight SCLK cycles. A burst read transaction is also demonstrated in Figure 5. First Bit ...
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... Si4430 3.2. Operating Mode Control There are four primary states in the Si4430 radio state machine: SHUTDOWN, IDLE, TX, and RX (see Figure 6). The SHUTDOWN state completely shuts down the radio to minimize current consumption. There are five different configurations/options for the IDLE state which can be selected to optimize the chip to the applications needs. ...
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... This mode of operation is designed for Frequency Hopping Systems (FHS). Tune mode is entered by setting pllon = 1 in "Register 07h. Operating Mode and Function Control 1" not necessary to set xton to 1 for this mode, the internal state machine automatically enables the crystal oscillator. Preliminary Rev. 0.4 Si4430 21 ...
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... Si4430 3.2.3. TX State The TX state may be entered from any of the IDLE modes when the txon bit is set "Register 07h. Operating Mode and Function Control 1". A built-in sequencer takes care of all the actions required to transition between states from enabling the crystal oscillator to ramping up the PA to prevent unwanted spectral splatter. The following sequence of events will occur automatically when going from STANDBY mode to TX mode by setting the txon bit ...
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... Interrupts The Si4430 is capable of generating an interrupt signal when certain events occur. The chip notifies the microcontroller that an interrupt event has been detected by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers 03h– ...
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... Si4430 3.5. System Timing The system timing for TX and RX modes is shown in Figures 8 and 7. The timing is shown transitioning from STANDBY mode to TX mode and going automatically through the built-in sequencer of required steps small range of frequencies is being used and the temperature range is fairly constant a calibration may only be needed at the initial power up of the device ...
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... XTAL Settling Time 600us Figure 8. RX Timing Preliminary Rev. 0.4 Si4430 RX Packet 25 ...
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... In order to receive or transmit an RF signal, the desired channel frequency, fcarrier, must be programmed into the Si4430. Note that this frequency is the center frequency of the desired channel and not an LO frequency. The carrier frequency is generated by a Fractional-N Synthesizer, using 20 MHz both as the reference frequency and ...
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... RX/TX modes. 3.6.2. Easy Frequency Programming for FHSS While Registers 73h–77h may be used to program the carrier frequency of the Si4430 often easier to think in terms of “channels” or “channel numbers” rather than an absolute frequency value in Hz. Also, there may be some timing-critical applications (such as for Frequency Hopping Systems) in which it is desirable to change frequency by programming a single register. Once the channel step size is set, the frequency may be changed by a single register corresponding to the channel number. A nominal frequency is first set using Registers 73h– ...
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... Si4430 The previous equation should be used to calculate the desired frequency deviation. If desired, frequency modulation may also be disabled in order to obtain an unmodulated carrier signal at the channel center frequency; see "4.1. Modulation Type" on page 32 for further details. Add R/W Function/Description 71 R/W Modulation Mode Control 2 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] ...
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... DesiredOff set 156 . hbsel ) 1 fo DesiredOff set 312 fo[6] fo[5] fo[4] (Rb = 100 kHz kHz) - Frequency Offset (kHz) Preliminary Rev. 0.4 Si4430 [ : POR Def. fo[3] fo[2] fo[1] fo[0] 00h fo[9] fo[8] 00h AFC Disable AFC Enable 100 Notes 73 29 ...
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... Si4430 “Register 1Dh. AFC Loop Gearshift Override,” on page 99), the Frequency Offset shows the results of the AFC algorithm for the current receive slot. When selecting the preamble length, the length needs to be long enough to settle the AFC. In general two bytes of preamble is sufficient to settle the AFC. Disabling the AFC allows the preamble to be shortened by about 8 bits. Note that with the AFC disabled, the preamble length must still be long enough to settle the receiver and to detect the preamble (see " ...
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... TX Data Rate 0 txdr [ MHz txdtrtscal e 2 txdtrtscal txdr [ MHz txdr[15] txdr[14] txdr[13] txdr[12] txdr[11] txdr[7] txdr[6] txdr[5] txdr[4] txdr[3] Preliminary Rev. 0.4 Si4430 POR Def. txdr[10] txdr[9] txdr[8] 0Ah txdr[2] txdr[1] txdr[0] AAh 31 ...
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... Modulation Options 4.1. Modulation Type The Si4430 supports three different modulation options: Gaussian Frequency Shift Keying (GFSK), Frequency Shift Keying (FSK), and On-Off Keying (OOK). GFSK is the recommended modulation type as it provides the best performance and cleanest modulation spectrum. Figure 11 demonstrates the difference between FSK and GFSK for a Data Rate of 64 kbps ...
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... Modulation Data Source The Si4430 may be configured to obtain its modulation data from one of three different sources: FIFO mode, Direct Mode, and from a PN9 mode. Furthermore, in Direct Mode, the TX modulation data may be obtained from several different input pins. These options are set through the dtmod[1:0] field in "Register 71h. Modulation Mode Control 2" ...
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... Si4430 4.5. PN9 Mode In this mode the TX Data is generated internally using a pseudorandom (PN9 sequence) bit generator. The primary purpose of this mode is for use as a test mode to observe the modulated spectrum without having to load/provide data. 4.6. Synchronous vs. Asynchronous In Asynchronous mode no clock is used to synchronize the data to the internal modulator. This mode can only be used with FSK. The advantage of this mode that it saves a microcontroller pin because no data clock is required. The disadvantage is that you don’ ...
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... SCLK VDD_RF TX SDI RXp SDO Matching RXn VDD_DIG VR_IF NC Figure 14. FIFO Mode Example Preliminary Rev. 0.4 nIRQ nSEL FIFO mode utilizing internal packet SCK handler. Data loaded/read through SPI MOSI into FIFO. C MISO GPIO configuration Not Utilized Si4430 35 ...
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... Si4430 5. Internal Functional Blocks This section provides an overview some of the key blocks of the internal radio architecture. 5.1. RX LNA The input frequency range for the LNA is 900–960 MHz. The LNA provides gain with a noise figure low enough to suppress the noise of the following stages. The LNA has one step of gain control which is controlled by the analog gain control (AGC) algorithm ...
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... These parameters may be adjusted via registers as shown in "3.6. Frequency Control" on page 26. Fref = 10 M PFD Figure 15. PLL Synthesizer Block Diagram CP LPF VCO N Delta- TX Modulation Sigma Preliminary Rev. 0.4 Si4430 TM is integrated to TX Selectable RX Divider 37 ...
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... In certain fast hopping applications this might not be desirable so the VCO calibration may be skipped by setting the appropriate register. 5.7. Power Amplifier The Si4430 contains an internal integrated power amplifier (PA) capable of transmitting at output levels between –8 to +13 dBm. The output power is programmable steps through the txpow[2:0] field in "Register 6Dh. TX Power". ...
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... Crystal Oscillator The Si4430 includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than 600 µs when a suitable parallel resonant crystal is used. The design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external components. By default, all that is required off-chip is the 30 MHz crystal blank ...
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... Si4430 6. Data Handling and Packet Handler 6.1. RX and TX FIFOs Two 64 byte FIFOs are integrated into the chip, one for RX and one for TX, as shown in Figure 16. "Register 7Fh. FIFO Access" is used to access both FIFOs. A burst write, as described in "3.1. Serial Peripheral Interface (SPI)" ...
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... The fields needed for packet generation normally change infrequently and can therefore be stored in registers. Automatically adding these fields to the data payload greatly reduces the amount of communication between the microcontroller and the Si4430 and therefore also reduces the required computational power of the microcontroller. ...
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... Si4430 6.3. Packet Handler TX Mode If the TX packet length is set the packet handler will send the number of bytes in the packet length field before returning to ready mode and asserting the packet sent interrupt. To resume sending data from the FIFO the microcontroller needs to command the chip to re-enter TX mode Figure 18 provides an example transaction where the packet length is set to three bytes ...
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... Data Data Write Pointer H L Data 63 63 set option set option set — set — set — — — for sync-detection Preliminary Rev. 0.4 Si4430 FIFO Addr Data H L Data Write H Pointer L Data Write CRC Pointer error 63 option Option option — ...
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... Si4430 Add R/W Function/Description D7 30 R/W Data Access Control enpacrx 31 R EzMAC status 32 R/W Header Control 1 bcen[3] 33 R/W Header Control 2 Reserved 34 R/W Preamble Length prealen[7] 35 R/W Preamble Detection Control preath[4] 36 R/W Sync Word 3 sync[31] 37 R/W Sync Word 2 sync[23] 38 R/W Sync Word 1 ...
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... Figure 22. Operation of Data Whitening, Manchester Encoding, and CRC 6.6. Preamble Detector The Si4430 has integrated automatic preamble detection. The preamble length is configurable from 1–256 bytes using the prealen[7:0] field in "Register 33h. Header Control 2" and "Register 34h. Preamble Length", as described in “6.2. Packet Configuration”. The preamble detection threshold, preath[4:0] as set in "Register 35h. Preamble Detection Control 1" ...
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... Antenna Diversity algorithm is allowed to complete. 6.9. TX Retransmission and Auto TX The Si4430 is capable of automatically retransmitting the last packet in the FIFO if no additional packets were loaded into the TX FIFO. Automatic Retransmission is achieved by entering the TX state with the txon bit set. This feature is useful for Beacon transmission or when retransmission is required due to the absence of a valid acknowledgement ...
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... Preliminary Rev. 0.4 Si4430 rxosr[10:0] ncoff[19:0] crgain[10:0] 20,21h 21,22,23h 24,25h 0FA 08312 06B 0D0 09D49 0A0 683 013A9 005 068 13A93 278 341 02752 00A 068 13A93 4EE 1A1 04EA5 024 064 147AE 521 190 051EC 02B 068 13A93 4EE 064 ...
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... Si4430 7.1.1. Advanced FSK and GFSK Settings In nearly all cases, the information in Table 16, “RX Modem Configurations for FSK and GFSK,” on page 47 can be used to determine the required FSK and GFSK modem parameters. The section includes a more detailed discussion of the various modem parameters to allow for experienced designers to further configure the modem performance ...
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... BW [kHz] ndec_exp 1C-[3:0] 1C-[6: 112 127 137 142 167 181 191 225 248 269 284 335 361 420 468 518 577 620 Preliminary Rev. 0.4 Si4430 dwn3_bypass filset 1C-[7] 1C-[3: ...
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... Si4430 7.2. Modem Settings for OOK The Si4430 is configured for OOK mode by setting the modtyp[1:0] field to OOK in "Register 71h. Modulation Mode Control 2". In OOK mode, the following parameters can be configured: data rate, manchester coding, channel filter bandwidth, and the clock recovery oversampling rate. ...
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... enmanch 20 ndec enmanch ) 2 500 1 2 dwn 3 _ bypass 16 2 2 crgain rxosr Preliminary Rev. 0.4 Si4430 exp 51 ...
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... Si4430 Table 20. RX Modem Configuration for OOK with Manchester Disabled RX Modem Setting Examples for OOK (Manchester Disabled) Appl Parameters dwn3_bypass [kbps] [kHz] 1Ch 1 1.2 110 0 1.2 335 1 1.2 420 1 1.2 620 1 2.4 335 1 4.8 335 1 9.6 335 1 10 335 1 15 335 1 19 ...
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... Auxiliary Functions 8.1. Smart Reset The Si4430 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a classic level threshold reset as well as a slope detector POR. This reset circuit was designed to produce reliable reset signal in any circumstances. Reset will be initiated if any of the following conditions occur: Initial power on, when VDD starts from 0V: reset is active till VDD reaches V ...
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... If the microcontroller clock option is being used there may be the need of a System Clock for the microcontroller while the Si4430 is in SLEEP mode. Since the Crystal Oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock. This feature is called Enable Low Frequency Clock and is enabled by the enlfc bit ...
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... Vin ADCSEL<2:0> Vref 0-1020mV / 0-255 BAT Ref MUX BAT REFSEL<1:0> adcsel[2] adcsel[1] adcsel[0] adcref[1] adcoffs[3] adc[7] adc[6] adc[5] adc[4] adc[3] Preliminary Rev. 0.4 Si4430 8-bit ADC VMEAS<7:0> POR Def. adcref[0] adcgain[1] adcgain[0] 00h adcoffs[2] adcoffs[1] adcoffs[0] 00h adc[2] adc[1] adc[0] — 55 ...
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... Si4430 8.3.1. ADC Differential Input Mode—Bridge Sensor Example The differential input mode of ADC8 is designed to directly interface any bridge-type sensor, which is demonstrated in the figure below. As seen in the figure the use of the ADC in this configuration will utilize two GPIO pins. The supply source of the bridge and chip should be the same to eliminate the measuring error caused by battery discharging ...
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... The offset compensation is VDD proportional, so the VDD change has no influence on the measured value. adcoffs[ Input Offset 0. –0.84 % Figure 26. ADC Differential Input Offset for Sensor Offset Coarse Compensation Input Offset (% of VDD adcoffs[2: –(8 – adcoffs[2:0]) x 0.12 adcoffs[2:0] x 0.12 8 Preliminary Rev. 0.4 Si4430 adcoffs[3: ...
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... Si4430 8.4. Temperature Sensor An analog temperature sensor is integrated into the chip. The temperature sensor will be automatically enabled when the temperature sensor is selected as the input of the ADC or when the analog temp voltage is selected on the analog test bus. The temperature sensor value may be digitized using the general-purpose ADC and read out over the SPI through " ...
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... Temperature Measurement with ADC8 300 250 200 150 100 50 0 -40 - Temperature [Celsius] Figure 27. Temperature Ranges using ADC8 Preliminary Rev. 0.4 Sensor Range 0 Sensor Range 1 Sensor Range 2 Sensor Range 100 Si4430 59 ...
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... Si4430 8.5. Low Battery Detector A low battery detector (LBD) with digital read-out is integrated into the chip. A digital threshold may be programmed into the lbdt[4:0] field in "Register 1Ah. Low Battery Detector Threshold". When the digitized battery voltage reaches this threshold an interrupt will be generated on the nIRQ pin to the microcontroller. The microcontroller will then need to verify the interrupt by reading " ...
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... M Value in Formula wtr[4] wtr[3] wtm[7] wtm[6] wtm[5] wtm[4] wtm[3] wtv[15] wtv[14] wtv[13] wtv[12] wtv[11] wtv[7] wtv[6] wtv[5] wtv[4] wtv[3] Preliminary Rev. 0.4 Si4430 POR Def. wtr[2] wtr[1] wtr[0] 03h 00h wtm[2] wtm[1] wtm[0] 00h wtv[10] wtv[9] wtv[8] — wtv[2] wtv[1] wtv[0] — ...
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... Si4430 WUT Period GPIOX=00001 nIRQ SPI Interrupt Read Chip State Sleep Ready 1mA Current Consumption WUT Period GPIOX=00001 nIRQ SPI Interrupt Read Chip State Current Consumption Figure 28. WUT Interrupt and WUT Operation 62 Interrupt Enable enwut=1 (Reg 06h) Sleep Ready Sleep 1mA ...
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... The time of the TLDC is determined by the formula below: TLDC ldc 768 Figure 29. Low Duty Cycle Mode Preliminary Rev. 0.4 Si4430 ms 63 ...
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... Si4430 8.8. GPIO Configuration Three general purpose IOs (GPIOs) are available. Numerous functions such as specific interrupts, TRSW control, Microcontroller Output, etc. can be routed to the GPIO pins as shown in the tables below. When in Shutdown mode all the GPIO pads are pulled low. Note: The ADC should not be selected as an input to the GPIO in Standby or Sleep Modes and will cause excess current con- sumption ...
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... Antenna Diversity Algorithm in Beacon Mode 111 Antenna Diversity Algorithm in Beacon Mode antdiv[2] antdiv[1] antdiv[0] rxmpk Table 24. Antenna Diversity Control RX/TX State GPIO Ant2 Preliminary Rev. 0.4 Si4430 POR Def. autotx enldm ffclrrx ffclrtx 00h Non RX/TX State GPIO Ant1 GPIO Ant2 ...
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... Si4430 8.10. RSSI and Clear Channel Assessment The RSSI (Received Signal Strength Indicator) signal is an estimate of the signal strength in the channel to which the receiver is tuned. The RSSI value can be read from an 8-bit register with 0.5 dB resolution per bit. Figure 30 demonstrates the relationship between input power level and RSSI value. The RSSI may be read at anytime, but an incorrect error may rarely occur ...
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... Reference Design Preliminary Rev. 0.4 Si4430 67 ...
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... Capacitor C14 100 pF Capacitor C15 1 µF Capacitor C18 100 nF Capacitor C23 100 nF Capacitor CS1 CON40-0 CON40-0 C_M * Capacitor C_M2 * Capacitor C_M3 * Capacitor IC1 Si4430 Si4430 IC2 25AA080-I/ST 25AA080ST L0 * Inductor L1 * Inductor L6 * Inductor L7 * Inductor L_M * Inductor L_M2 * Resistor Q1 30 MHz Crystal Q2 32.7 kHz ...
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... Note: Sensitivity is BER measured, GFSK modulation 0. Sensitivity vs. Data Rate Measured at RX SMA Connector Input 10 kbps Data Rate Figure 32. Sensitivity vs. Data Rate Preliminary Rev. 0.4 Si4430 100 kbps 1000 kbps 69 ...
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... Si4430 Adjacent Channel Selectivity at 50 kbps Measured at RX SMA Connector Input -10 dB -20 dB -30 dB -40 dB -50 dB -60 dB -1.00 -0.75 MHz MHz Adjacent Channel Selectivity at 50 kbps (log scale) Measured at RX SMA Connector Input -10 dB -20 dB -30 dB -40 dB -50 dB -60 dB -70 dB -80 dB ...
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... Si4430 Figure 34. TX Modulation (40 kbps, 20 kHz Deviation) Figure 35. TX Unmodulated Spectrum (917 MHz) Preliminary Rev. 0.4 Si4430 71 ...
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... Si4430 Figure 36. TX Modulated Spectrum (917 MHz, 40 kbps, 20 kHz Deviation, GFSK) Si4430 Figure 37. Synthesizer Settling Time for 1 MHz Jump Settled within 10 kHz 72 Preliminary Rev. 0.4 ...
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... Figure 38. Synthesizer Phase Noise (VCOCURR = 11) Preliminary Rev. 0.4 Si4430 73 ...
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... Si4430 11. Application Notes This section offers a brief introduction to a number of application related topics. Further recommended reading can be found in our related application notes at http://www.silabs.com. 11.1. Crystal Selection The recommended crystal parameters are given in Table 26. Table 26. Recommended Crystal Parameters Frequency ESR 30 MHz 60 Ω ...
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... Preliminary Rev. 0.4 Si4430 Data dt[3] dt[2] dt[1] vc[3] vc[2] vc[1] reserved reserved cps[1] cps[0] iext ipksent ipkvalid icrcerror iwut ilbd ...
Page 76
... Si4430 Add R/W Function/Desc 3D R/W Transmit Header 0 3E R/W Transmit Packet Length 3F R/W Check Header 3 40 R/W Check Header 2 41 R/W Check Header 1 42 R/W Check Header 0 43 R/W Header Enable 3 44 R/W Header Enable 2 45 R/W Header Enable 1 46 R/W ...
Page 77
... EZRadioPRO: 01000. Register 01h. Version Code (VC) Bit D7 D6 Reserved Name R Type Reset value = xxxxxxxx Bit Name 7:5 Reserved Reserved. 4:0 vc[4:0] Version Code. Code indicating the version of the chip. Rev A0: 00100 Rev V2: 00011 Function Function Preliminary Rev. 0.4 Si4430 dt[4: vc[4: ...
Page 78
... Si4430 Register 02h. Device Status Bit D7 D6 ffovfl ffunfl Name R R Type Reset value = xxxxxxxx Bit Name 7 ffovfl RX/TX FIFO Overflow Status. 6 ffunfl RX/TX FIFO Underflow Status. 5 rxffem RX FIFO Empty Status. 4 headerr Header Error Status. Indicates if the received packet has a header check error. ...
Page 79
... If any of these bits is not enabled in the Interrupt Enable 1 register then it becomes a status signal that can be read anytime in the same location and will not be cleared by reading the register ixtffaem irxffafull iext Function Preliminary Rev. 0.4 Si4430 ipksent ipkvalid icrerror ...
Page 80
... Si4430 Table 28. Interrupt or Status 1 Bit Set/Clear Description Bit Status Name 7 ifferr Set if there is a FIFO overflow or underflow. Cleared by applying FIFO reset. 6 itxffafull Set when the number of bytes written to TX FIFO is greater than the Almost Full threshold. Automatically cleared at the start of transmission when the number of bytes in the FIFO is less than or equal to the threshold ...
Page 81
... HIGH and all the enabled interrupt bits will be cleared when the microcontroller reads this address. If any of these bits is not enabled in the Interrupt Enable 2 register then it becomes a status signal that can be read anytime in the same location and will not be cleared by reading the register ipreainval irssi iwut Function Preliminary Rev. 0.4 Si4430 ilbd ichiprdy ipor ...
Page 82
... Si4430 Table 30. Interrupt or Status 2 Bit Set/Clear Description Bit Status Name 7 iswdet Goes high once the Sync Word is detected. Goes low once we are done receiving the cur- rent packet. 6 ipreaval Goes high once the preamble is detected. Goes low once the sync is detected or the RX wait for the sync times-out ...
Page 83
... Enable Valid Packet Received. When ipkvalid = 1 the Valid Packet Received Interrupt will be enabled. 0 encrcerror Enable CRC Error. When set to 1 the CRC Error interrupt will be enabled entxffaem enrxffafull enext R/W R/W R/W Function Preliminary Rev. 0.4 Si4430 enpksent enpkvalid encrcerror R/W R/W R/W 83 ...
Page 84
... Si4430 Register 06h. Interrupt Enable 2 Bit D7 D6 enswdet enpreaval Name R R Type Reset value = 00000011 Bit Name 7 enswdet Enable Sync Word Detected. When mpreadet =1 the Preamble Detected Interrupt will be enabled. 6 enpreaval Enable Valid Preamble Detected. When mpreadet =1 the Valid Preamble Detected Interrupt will be enabled. ...
Page 85
... When pllon = 1 the PLL will remain enabled in Idle State. This will for faster turn-around time at the cost of increased current consumption in Idle State. 0 xton READY Mode (Xtal is ON enwt x32ksel txon R/W R/W R/W Function Preliminary Rev. 0.4 Si4430 rxon pllon xton R/W R/W R/W 85 ...
Page 86
... Si4430 Register 08h. Operating Mode and Function Control 2 Bit D7 D6 antdiv[2:0] Name R/W Type Reset value = 00000000 Bit Name 7:5 antdiv[2:0] Enable Antenna Diversity. The GPIO must be configured for Antenna Diversity for the algorithm to work properly. RX/TX state GPIO Ant1 000: ...
Page 87
... Register 09h. 30 MHz Crystal Oscillator Load Capacitance Bit D7 D6 xtalshft Name R/W Type Reset value = 01111111 Bit Name 7 xtalshft Additional capacitance to course shift the frequency if xlc[6:0] is not sufficient. Not binary with xlc[6:0]. 6:0 xlc[6:0] Tuning Capacitance for the 30 MHz XTAL xlc[6:0] R/W Function Preliminary Rev. 0.4 Si4430 ...
Page 88
... Si4430 Register 0Ah. Microcontroller Output Clock Bit D7 D6 Reserved Name R Type Reset value = xx000110 Bit Name 7:6 Reserved Reserved. 5:4 clkt[1:0] Clock Tail. If enlfc = 0 then it can be useful to provide a few extra cycles for the microcontroller to complete its operation. Setting the clkt[1:0] register will provide the addition cycles of the clock before it shuts off ...
Page 89
... Antenna 2 Switch used for antenna diversity (output) 11001: Valid Preamble Detected (output) 11010: Invalid Preamble Detected (output) 11011: Sync Word Detected (output) 11100: Clear Channel Assessment (output) 11101: VDD else : GND pup0 R/W Function Preliminary Rev. 0.4 Si4430 gpio0[4:0] R/W 89 ...
Page 90
... Si4430 Register 0Ch. GPIO Configuration 1 Bit D7 D6 gpiodrv1[1:0] Name R/W Type Reset value = 00000000 Bit Name 7:6 gpiodrv1[1:0] GPIO Driving Capability Setting. 5 pup1 Pullup Resistor Enable on GPIO1. When set to 1 the a 200 kresistor is connected internally between VDD and the pin if the GPIO is configured as a digital input ...
Page 91
... Antenna 2 Switch used for antenna diversity (output) 11001: Valid Preamble Detected (output) 11010: Invalid Preamble Detected (output) 11011: Sync Word Detected (output) 11100: Clear Channel Assessment (output) 11101: VDD else : GND pup2 R/W Function Preliminary Rev. 0.4 Si4430 gpio2[4:0] R/W 91 ...
Page 92
... Si4430 Register 0Eh. I/O Port Configuration Bit D7 D6 Reserved extitst[2] Name R R Type Reset value = 00000000 Bit Name 7 Reserved Reserved. 6 extitst[2] External Interrupt Status. If the GPIO2 is programmed to be external interrupt sources then the status can be read here. 5 extitst[1] External Interrupt Status. ...
Page 93
... ADC Sensor Amplifier Gain Selection. The full scale range of the internal 8-bit ADC in differential mode (see adcsel) can be set as follows: adcref[ 0.014 x (adcgain[1: VDD FS = 0.021 x (adcgain[1: VDD adcsel[2:0] adcref[1:0] R/W Function adcref[ Preliminary Rev. 0.4 Si4430 adcgain[1:0] R/W R/W 93 ...
Page 94
... Si4430 Register 10h. ADC Sensor Amplifier Offset Bit D7 D6 Reserved Name R Type Reset value = xxxx0000 Bit Name 7:4 Reserved Reserved. 3:0 adcoffs[3:0] ADC Sensor Amplifier Offset*. *Note: The offset can be calculated as Offset = adcoffs[2:0] x VDD / 1000; MSB = adcoffs[3] = Sign bit. Register 11h. ADC Value ...
Page 95
... Bit Name 7:0 tvoffs[7:0] Temperature Value Offset. This value is added to the measured temperature value. (MSB, tvoffs[8]: sign bit entsoffs entstrim R/W R/W Function 0 C, with 0.5 C resolution (1 LSB in the 8-bit ADC tvoffs[7:0] R/W Function Preliminary Rev. 0.4 Si4430 tstrim[3:0] R ...
Page 96
... Si4430 Note new configuration is needed (e.g., for the WUT or the LDC), proper functionality is required. The function must first be disabled, then the settings changed, then enabled back on. Register 14h. Wake-Up Timer Period 1 Bit D7 D6 Reserved Name R/W Type Reset value = xxx00011 Bit ...
Page 97
... The period of the low-duty cycle ON time can be calculated the wake-up timer setting in "Register 14h. Wake-Up Timer Period 1" wtm[15:8] R Function 32.768 ms. WUT wtm[7:0] R Function 32.768 ms. WUT ldc[7:0] R/W Function = (4 x LDC x 2 LDC_ON Preliminary Rev. 0.4 Si4430 32.768 ms the same 97 ...
Page 98
... Si4430 Register 1Ah. Low Battery Detector Threshold Bit D7 D6 Reserved Name R Type Reset value = xxx10100 Bit Name 7:5 Reserved Reserved. 4:0 lbdt[4:0] Low Battery Detector Threshold. This threshold is compared to Battery Voltage Level. If the Battery Voltage is less than the threshold the Low Battery Interrupt is set. Default = 2.7 V.* *Note: The threshold can be calculated as V Register 1Bh ...
Page 99
... Reset value = 01000000 Bit Name 7 afcbd If set, the tolerated AFC frequency error will be halved. 6 enafc AFC Enable. 5:3 afcgearh[2:0] AFC High Gear Setting. 2:0 afcgearl[2:0] AFC Low Gear Setting ndec_exp[2:0] R/W Function afcgearh[2:0] R/W Function Preliminary Rev. 0.4 Si4430 filset[3:0] R afcgearl[2:0] R/W 99 ...
Page 100
... Si4430 Register 1Eh. AFC Timing Control Bit D7 D6 Reserved Name R Type Reset value = xx001010 Bit Name 7:6 Reserved Reserved. 5:3 shwait[2:0] Short Wait Periods after AFC Correction. Used before preamble is detected. Short wait = (RegValue + AFC correction will occur before preamble detect, i.e. AFC will be disabled. ...
Page 101
... Once the preamble is detected, internal state machine automatically shift BCR loop gain to the following: crfast = 3’b000 and crslow = 3’b101 are recommended for most applications. The value of “crslow” should be greater than “crfast” crfast[2:0] R/W Function crgain BCRLoopGai n crfast 2 crgain BCRLoopGai n crslow 2 Preliminary Rev. 0.4 Si4430 crslow[2:0] R/W 101 ...
Page 102
... Si4430 Register 20h. Clock Recovery Oversampling Rate Bit D7 D6 Name Type Reset value = 01100100 Bit Name 7:0 rxosr[7:0] Oversampling Rate. 3 LSBs are the fraction, default = 0110 0100 = 12.5 clock cycles per data bit The oversampling rate can be calculated as rxosr = 500 kHz/(2 dwn3_bypass values found at Address: 1Ch – ...
Page 103
... Bit Name 7:0 ncoff[15:8] NCO Offset. See formula above stallctrl R/W Function 20 ndec enmanch ) 2 ncoff 500 1 2 dwn 3 _ bypass ncoff[15:8] R/W Function Preliminary Rev. 0.4 Si4430 ncoff[19:16] R/W _ exp 103 ...
Page 104
... Si4430 Register 23h. Clock Recovery Offset 0 Bit D7 D6 Name Type Reset value = 10101110 Bit Name 7:0 ncoff[7:0] NCO Offset. See formula above Register 24h. Clock Recovery Timing Loop Gain 1 Bit D7 D6 Name Type Reset value = 00000010 Bit Name 7:3 Reserved Reserved. ...
Page 105
... RSSI Threshold. Interrupt is set if the RSSI value is above this threshold. Register 28h. Antenna Diversity 1 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 adrssi[7:0] Measured RSSI Value on Antenna rssi[7:0] R Function rssith[7:0] R/W Function adrssi[7:0] R Function Preliminary Rev. 0.4 Si4430 105 ...
Page 106
... Si4430 Register 29h. Antenna Diversity 2 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 adrssi2[7:0] Measured RSSI Value on Antenna 2. Register 2Ah. AFC Limiter Bit D7 D6 Name Type Reset value = 00101010 Bit Name 7:0 Afclim[7:0] AFC Limiter. AFC limiter value. For the following registers (addresses 2Bh and 2Ch), use the following equation: where Rb's unit is in kHz and “ ...
Page 107
... Register 2Dh. OOK Counter Value 2 Bit D7 D6 Name Type Reset value = 00101101 Bit Name 7:0 afc_corr[9:2] OOK Counter [7:0]. OOK counter value LSBs ookfrzen peakdeten madeten R/W R/W R/W Function ookcnt[7:0] R/W Function Preliminary Rev. 0.4 Si4430 ookcnt[10] ookcnt[9] ookcnt[8] R/W R/W R 107 ...
Page 108
... Si4430 Register 2Eh. Slicer Peak Holder Bit D7 D6 Reserved Name R/W Type Reset value = 00101110 Bit Name 7 Reserved Reserved. 6:4 attack[2:0] Attack. 3:0 decay[3:0] Decay. 108 attack[2:0] R/W Function Preliminary Rev. 0 decay[3:0] R/W ...
Page 109
... TX path. It will only transmit what is loaded to the FIFO. 2 encrc CRC Enable. Cyclic Redundancy Check generation is enabled if this bit is set. 1:0 crc[1:0] CRC Polynomial Selection. 00: CCITT 01: CRC-16 (IBM) 10: IEC-16 11: Biacheva crcdonly Reserved enpactx R/W R/W R/W Function Preliminary Rev. 0.4 Si4430 encrc crc[1:0] R/W R/W 109 ...
Page 110
... Si4430 ® Register 31h. EZMAC Status Bit D7 D6 Reserved rxcrc1 Name R R Type Reset value = 00000000 Bit Name 7 Reserved Reserved. 6 rxcrc1 If high, it indicates the last CRC received is all one’s. May indicated Transmitter underflow in case of CRC error. Packet Searching . 5 pksrch When pksrch = 1 the radio is searching for a valid packet. ...
Page 111
... Broadcast address enable for header byte 1. Broadcast address enable for header bytes 0 & 1. … No Received Header check Received Header check for byte 0. Received Header check for bytes 1. Received header check for bytes 0 & 1. … Preliminary Rev. 0.4 Si4430 hdch[3:0] R/W 111 ...
Page 112
... Si4430 Register 33h. Header Control 2 Bit D7 D6 Reserved Name R Type Reset value = 00100010 Bit Name 7 Reserved Reserved. 6:4 hdlen[2:0] Header Length. Length of header used if packet handler is enabled for TX/RX (enpactx/rx). Headers are transmitted/received in descending order. 000: 001: 010: 011: 100: 3 fixpklen Fix Packet Length ...
Page 113
... Reset value = 00101010 Bit Name 7:3 preath[4:0] Number of nibbles processed during detection. 2:0 rssi_offset[2:0] rssi_offset[2:0] Value added as offset to RSSI calculation. Every increment in this register results in an increment the RSSI prealen[7:0] R/W Function preath[4:0] R/W Function Preliminary Rev. 0.4 Si4430 rssi_offset[2:0] R/W 113 ...
Page 114
... Si4430 Register 36h. Synchronization Word 3 Bit D7 D6 Name Type Reset value = 00101101 Bit Name 7:0 sync[31:24] Synchronization Word byte of the synchronization word. Register 37h. Synchronization Word 2 Bit D7 D6 Name Type Reset value = 11010100 Bit Name 7:0 sync[23:16] Synchronization Word byte of the synchronization word. ...
Page 115
... Register 3Bh. Transmit Header 2 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 txhd[23:16] Transmit Header byte of the header to be transmitted sync[7:0] R/W Function txhd[31:24] R/W Function txhd[23:16] R/W Function Preliminary Rev. 0.4 Si4430 115 ...
Page 116
... Si4430 Register 3Ch. Transmit Header 1 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 txhd[15:8] Transmit Header byte of the header to be transmitted. Register 3Dh. Transmit Header 0 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 txhd[7:0] Transmit Header byte of the header to be transmitted ...
Page 117
... Check Header byte of the check header. Register 41h. Check Header 1 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 chhd[15:8] Check Header byte of the check header chhd[31:24] R/W Function chhd[23:16] R/W Function chhd[15:8] R/W Function Preliminary Rev. 0.4 Si4430 117 ...
Page 118
... Si4430 Register 42h. Check Header 0 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 chhd[7:0] Check Header byte of the check header. Header Enable bytes control which bits of the Check Header bytes are checked against the corresponding bits in the Received Header. Only those bits are compared where the enable bits are set to 1. ...
Page 119
... Header Enable byte of the check header. Register 47h. Received Header 3 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 rxhd[31:24] Received Header byte of the received header hden[15:8] R/W Function hden[7:0] R/W Function rxhd[31:24] R Function Preliminary Rev. 0.4 Si4430 119 ...
Page 120
... Si4430 Register 48h. Received Header 2 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 rxhd[23:16] Received Header byte of the received header. Register 49h. Received Header 1 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 rxhd[15:8] Received Header byte of the received header. ...
Page 121
... Name R/W Type Reset value = 00000000 Bit Name 7:5 Reserved Reserved. 4:0 atb[4:0] Analog Test Bus. The selection of internal analog testpoints that are muxed onto TESTp and TESTn rxplen[7:0] R Function adc8[5:0] R/W Function Function Preliminary Rev. 0.4 Si4430 atb[4:0] R/W 121 ...
Page 122
... Si4430 Table 32. Internal Analog Signals Available on the Analog Test Bus atb[4: 122 GPIOx GPIOx MixIp MixIn MixQp MixQn PGA_Ip PGA_In PGA_QP PGA_Qn ADC_vcm ADC_vcmb ADC_ipoly10u ADC_ref ADC_Refdac_p ADC_Refdac_n ADC_ipoly10 ADC_ipoly10 ADC_Res1Ip ADC_Res1In ADC_Res1Qp ADC_Res1Qn Reserved Reserved Reserved Reserved Reserved Reserved Reserved ...
Page 123
... VCO bias shunt enable frac_div_en fractional divider enable pll_pfd_down PFD down signal pll_en PLL enable: TUNE state pll_lock_detect PLL lock detect pwst[1] internal power state Preliminary Rev. 0.4 Si4430 GPIO2 Signal clk_base timebase clock tm1sec 1 sec timebase adc_done aux. ADC measurement done ...
Page 124
... Si4430 Table 33. Internal Digital Signals Available on the Digital Test Bus (Continued) dtb[4:0] GPIO0 Signal 30 xok chip ready: READY state 31 ts_en temperature sensor enable 32 ch_freq_req frequency change request 33 retran_req retransmission request 34 pa_on_trig PA ON trigger 35 tx_shdwn TX shutdown 36 pk_sent_dly delayed packet sent 37 tx_en TX enable: TX state ...
Page 125
... TX Ramp Time. The PA is ramped up slowly to prevent VCO pulling and spectral splatter. This register sets the time the PA is ramped up. 00: 5 µs 01: 10 µs 10: 15 µs 11: 20 µ txmod[2:0] ldoramp[1:0] R/W Function Preliminary Rev. 0.4 Si4430 txramp[1:0] R/W R/W 125 ...
Page 126
... Si4430 The total settling time (cold start) of the PLL after the calibration can be calculated as T Register 53h. PLL Tune Time Bit D7 D6 Name Type Reset value = 01010010 Bit Name 7:3 pllts[4:0] PLL Soft Settling Time (T This register will set the settling time for the PLL from a previous locked frequency in Tune mode. The value is configurable between 0 µ ...
Page 127
... VCO. This bit is cleared automatically. 0 skipvco Skip VCO Calibration. Setting skipvco = 1 will skip the VCO calibration when going from the Idle state to the state adccaldone enrcfcal rccal R R/W R/W Function Preliminary Rev. 0.4 Si4430 vcocaldp vcocal skipvco R/W R/W R/W 127 ...
Page 128
... Si4430 Register 56h. Modem Test Bit D7 D6 bcrfbyp slicfbyp Name R/W R/W Type Reset value = 00000000 Bit Name 7 bcrfbyp If set, BCR phase compensation will be bypassed. 6 slicfbyp If set, slicer phase compensation will be bypassed. 5 dttype Dithering Type. If low and dither enabled, we add +1/0, otherwise if high and dithering enabled, we add ± ...
Page 129
... Feedback (fractional) Divider High Current Enable (+5 µA). 5:4 d3trim[1:0] Divider 3 Current Trim Value. 3:2 d2trim[1:0] Divider 2 Current Trim Value. 1:0 d1p5trim[1:0] Divider 1.5 (div-by-1.5) Current Trim Value cpcorrov R/W Function d3trim[1:0] d2trim[1:0] R/W R/W Function Preliminary Rev. 0.4 Si4430 cporr[4:0] R d1p5trim[1:0] R/W 129 ...
Page 130
... Si4430 Register 5Ah. VCO Current Trimming Bit D7 D6 txcurboosten vcocorrov Name R/W R/W Type Reset value = 00000011 Bit Name 7 txcurboosten If this is Set, then vcocur = 11 during TX Mode and VCO CAL followed by TX. 6 vcocorrov VCO Current Correction Override. 5:2 vcocorr[3:0] VCO Current Correction Value. ...
Page 131
... Delta-Sigma Modulus 000 1: 65 536 3:2 dsorder[1:0] Delta-Sigma Order. 00: 0 order st 01 10: 2 11: Mash 111 1 dsrstmode Delta-Sigma Reset Mode. 0 dsrst Delta-Sigma Reset enoloop dsmod dsorder[1:0] R/W R/W Function order order Preliminary Rev. 0.4 Si4430 dsrstmode dsrst R/W R/W R/W 131 ...
Page 132
... Si4430 Register 5Dh. Block Enable Override 1 Bit D7 D6 enmix enina Name R/W R/W Type Reset value = 00000000 Bit Name 7 enmix Mixer Enable Override. 6 enlna LNA Enable Override. 5 enpga PGA Enable Override. 4 enpa Power Amplifier Enable Override. 3 enbf5 Buffer 5 Enable Override. 2 endv32 Divider 3_2 Enable Override ...
Page 133
... Name 7:4 Reserved Reserved. 3:0 chfiladd[3:0] Channel Filter Coefficient Look-up Table Address. The address for channel filter coefficients used in the RX path endv2 endv1p5 dvbshunt R/W R/W R/W Function Function Preliminary Rev. 0.4 Si4430 envco encp enbg R/W R/W R chfiladd[3:0] R/W 133 ...
Page 134
... Si4430 Register 61h. Channel Filter Coefficient Value Bit D7 D6 Reserved Name R/W Type Reset value = 00000000 Bit Name 7:6 Reserved Reserved. 5:0 chfilval[5:0] Filter Coefficient Value in the Look-up Table Addressed by the chfiladd[3:0]. Register 62h. Crystal Oscillator/Power-on-Reset Control Bit D7 D6 pwst[2:0] Name ...
Page 135
... When rcfov = 0 the internal Fine Calibration results may be viewed by reading the rcfcal register. When rcfov = 1 the Fine results may be overridden externally through the SPI by writing to the rcfcal register. 6:0 rcf[6:0] RC Oscillator Fine Calibration Override Value/Results rcc[6:0] R/W Function rcf[6:0] R/W Function Preliminary Rev. 0.4 Si4430 135 ...
Page 136
... Si4430 Register 65h. LDO Control Override Bit D7 D6 enspor enbias Name R/W R/W Type Reset value = 10000001 Bit Name 7 enspor Smart POR Enable. 6 enbias Bias Enable. 5 envcoldo VCO LDO Enable. 4 enifldo IF LDO Enable. 3 enrfldo RF LDO Enable. 2 enpllldo PLL LDO Enable. 1 endigldo Digital LDO Enable ...
Page 137
... Delta-Sigma ADC VCM Enable Override. 3 adcoloop Delta-Sigma ADC Open Loop Enable. 2:0 adcref[2:0] Delta-Sigma ADC Reference Voltage. 000: 0.5 V 001: 0.6 V 010: 0.7 V … 111: 1 enadc adctuneovr R/W R/W Function envcm adcoloop R/W R/W Function Preliminary Rev. 0.4 Si4430 adctune[3:0] R adcref[2:0] R/W 137 ...
Page 138
... Si4430 Register 69h. AGC Override 1 Bit D7 D6 Reserved Name R Type Reset value = 00100000 Bit Name 7:6 Reserved Reserved. 5 agcen Automatic Gain Control Enable. When this bit is set then the result of the control can be read out from bits [4:0], otherwise the gain can be controlled manually by writing into bits [4:0]. ...
Page 139
... D7 D6 Reserved Name R/W Type Reset value = xxxxx000 Bit Name 7:6 Reserved Reserved. 5:0 firval[5:0] FIR Coefficient Value in the lOok-up Table Addressed by the firadd[2:0]. The default coefficient can be read or modified Reserved R Function firval[5:0] Function Preliminary Rev. 0.4 Si4430 firadd[2:0] R R/W 139 ...
Page 140
... Si4430 Register 6Dh. TX Power Bit D7 D6 Reserved Name R Type Reset value = xxxx1000 Bit Name 7:4 Reserved Reserved. 3 lna_sw LNA Switch Controller. If set, lna_sw control from the digital will go high during TX modes, and low during other times. If reset, the digital control signal is low at all times. ...
Page 141
... Manchester Data Inversion is Enabled if this bit is set. 1 enmanch Manchester Coding is Enabled if this bit is set. 0 enwhite Data Whitening is Enabled if this bit is set txdr[7:0] R/W Function txdtrtscale enphpwdn manppol R/W R/W R/W Function Preliminary Rev. 0.4 Si4430 enmaninv enmanch enwhite R/W R/W R/W 141 ...
Page 142
... Si4430 Register 71h. Modulation Mode Control 2 Bit D7 D6 trclk[1:0] Name R/W Type Reset value = 00000000 Bit Name 7:6 trclk[1:0] TX Data Clock Configuration. 00 Data CLK is available (asynchronous mode – Can only work with modula- tions FSK or OOK). 01: TX Data CLK is available via the GPIO (one of the GPIO’s should be programmed as well) ...
Page 143
... Reading from this register will give the AFC correction last results, not this register value fd[7:0] R/W Function is the deviation and R is the data rate. When Manchester coding is enabled the fo[7:0] R/W Function Preliminary Rev. 0.4 Si4430 143 ...
Page 144
... Si4430 Register 74h. Frequency Offset 2 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:2 Reserved Reserved. 1:0 fo[9:8] Upper Bits of the Frequency Offset Setting. fo[9] is the sign bit. The frequency offset can be calculated as Offset = 312 fo[7:0]. fo[9: twos complement value. Reading from this register will give the AFC correc- tion last results, not this register value ...
Page 145
... If set, we will enable the alternative PA sequence. By default, this is not enabled. 2:0 rcosc_cal[2:0] rcosc_cal[2:0]. Fine changes on the RC OSC Calibration target frequency, to help compensate for “cali- bration biases.” This register should not be changed by costumers fc[15:8] R/W Function fc[7:0] R/W Function Alt_PA_Seq R/W Function Preliminary Rev. 0.4 Si4430 rcosc_cal[2:0] R/W 145 ...
Page 146
... Si4430 Register 79h. Frequency Hopping Channel Select Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 fhch[7:0] Frequency Hopping Channel Number. Register 7Ah. Frequency Hopping Step Size Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 fhs[7:0] Frequency Hopping Step Size in 10 kHz Increments. ...
Page 147
... Make sure it does not happen to early otherwise the last bits will be missed. Register 7Ch. TX FIFO Control 1 Bit D7 D6 Reserved Name R/W Type Reset value = 00110111 Bit Name 7:6 Reserved Reserved. 5:0 txafthr[5:0] TX FIFO Almost Full Threshold Reserved[6:3] turn_around_en R/W Function txafthr[5:0] R/W Function Preliminary Rev. 0.4 Si4430 phase[1:0] R/W R 147 ...
Page 148
... Si4430 Register 7Dh. TX FIFO Control 2 Bit D7 D6 Reserved Name R/W Type Reset value = 00000100 Bit Name 7:6 Reserved Reserved. 5:0 txfaethr[5:0] TX FIFO Almost Empty Threshold. Register 7Eh. RX FIFO Control Bit D7 D6 Reserved Name R/W Type Reset value = 00110111 Bit Name 7:6 Reserved Reserved ...
Page 149
... PKG PADDLE_GND GND The exposed metal paddle on the bottom of the Si4430 supplies the RF and circuit ground(s) for the entire chip very important that a good solder connection is made between this exposed metal paddle and the ground plane of the PCB underlying the Si4430. ...
Page 150
... Si4430 14. Ordering Information Part Number* Si4430-A0-FM ISM EZRadioPRO Transceiver *Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel. 150 Description Preliminary Rev. 0.4 Package Operating Type Temperature QFN-20 – °C Pb-free ...
Page 151
... Package Information Figure 39 illustrates the package details for the Si4430, and Figure 40 illustrates the landing pattern details. Figure 39. QFN-20 Package Dimensions Figure 40. QFN-20 Landing Pattern Dimensions Preliminary Rev. 0.4 Si4430 151 ...
Page 152
... Si4430 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: wireless@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...