CYRF7936-40LFXC Cypress Semiconductor Corp, CYRF7936-40LFXC Datasheet - Page 4

• Manufacturer Part Number: CYRF7936-40LFXC
• Description: IC CYFI TRANSCEIVER 40VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CyFi™r

Specifications of CYRF7936-40LFXC

• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 1Mbps
• Modulation Or Protocol: DSSS
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Interface Type: SPI
• Output Power: + 4 dBm
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Modulation: DSSS, GFSK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Applications: -
• Sensitivity: -
• Memory Size: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2273

CRC16 detects the following errors:
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Packet Buffers
All data transmission and reception use the 16 byte packet
buffers - one for transmission and one for reception.
The transmit buffer allows loading a complete packet of up to 16
bytes of payload data in one burst SPI transaction. This is then
transmitted with no further MCU intervention. Similarly, the
receive buffer allows receiving an entire packet of payload data
up to 16 bytes with no firmware intervention required until the
packet reception is complete.
Maximum packet length depends on the accuracy of the clock on
each end of the link. Packet lengths up to 40 bytes are supported
when the delta between the transmitter and receiver crystals is
60 ppm or better. Interrupts are provided to allow an MCU to use
the transmit and receive buffers as FIFOs. When transmitting a
packet longer than 16 bytes, the MCU can load 16 bytes initially,
and add further bytes to the transmit buffer as transmission of
data creates space in the buffer. Similarly, when receiving
packets longer than 16 bytes, the MCU must fetch received data
from the FIFO periodically during packet reception to prevent it
from overflowing.
Auto Transaction Sequencer (ATS)
The CYRF7936 IC provides automated support for transmission
and reception of acknowledged data packets.
When transmitting in transaction mode, the device automatically:
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Document Number: 001-48013 Rev*A
Any one bit in error.
Any two bits in error (irrespective of how far apart, which
column, and so on).
Starts the crystal and synthesizer
Enters transmit mode
Transmits the packet in the transmit buffer
Transitions to receive mode and waits for an ACK packet
Transitions to the transaction end state when an ACK packet
is received or a timeout period expires
P re a m b le
n x 1 6 u s
P
1 s t F ra m in g
P r e a m b l e
S y m b o l*
S O P 1
n x 1 6 u s
P
1 s t F r a m i n g
S O P 1
S y m b o l *
2 n d F ra m in g
S y m b o l*
S O P 2
2 n d F r a m i n g
S y m b o l *
S O P 2
L e n g th
P a c k e t
Figure 3. Example ACK Packet Format
1 B y te
P e rio d
le n g th
Figure 2. Example Packet Format
P a y lo a d D a ta
r e c e i v e d p a c k e t .
C R C f i e l d f r o m
2 B y t e p e r i o d s
C R C 1 6
■
■
Figure 2
lengths fields enabled, and
packet.
Similarly, when receiving in transaction mode, the device
automatically:
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■
■
The contents of the packet buffers are not affected by the
transmission or reception of ACK packets.
In each case, the entire packet transaction takes place without
any need for MCU firmware action (as long as packets of 16
bytes or less are used). To transmit data, the MCU must load the
data packet to be transmitted, set the length, and set the TX GO
bit. Similarly, when receiving packets in transaction mode,
firmware must retrieve the fully received packet in response to
an interrupt request indicating reception of a packet.
Data Rates
The CYRF7936 IC supports the following data rates by
combining the PN code lengths and data transmission modes
described in the previous sections:
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Any odd number of bits in error (irrespective of the location).
An error burst as wide as the checksum itself.
Waits in receive mode for a valid packet to be received
Transitions to transmit mode, transmits an ACK packet
Transitions to the transaction end state (receive mode to await
the next packet, and so on.)
1000 kbps (GFSK)
250 kbps (32 chip 8DR)
125 kbps (64 chip 8DR)
shows an example packet with SOP, CRC16, and
Figure 3
* N o t e : 3 2 o r 6 4 u s
shows a standard ACK
*N o te :3 2 o r 6 4 u s
C R C 1 6
CYRF7936
Page 4 of 21
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