TRC102 RFM, TRC102 Datasheet - Page 42

• Manufacturer Part Number: TRC102
• Description: RFIC TRANCEIVER MULTI-CHANNEL FS
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC102

• Frequency: 400MHz ~ 1GHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK
• Applications: General Purpose
• Power - Output: 5dBm
• Sensitivity: -112dBm
• Voltage - Supply: 2.2 V ~ 3.8 V
• Current - Receiving: 12mA
• Current - Transmitting: 23mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1094-2

PLL Configuration Register
The PLL Configuration Register configures the following:
Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor
that identifies the bits to be written to the PLL Configuration Register.
Bit [7] – Not Used: Write a ‘0’.
Bit [6..5] – Clock Buffer Slew: These bits set the rise and fall times for the clock buffer dependant on
the output frequency. See table 17 below.
Bit [4] – Crystal Start-up Time: This bit sets the start-up time and current consumption of the crystal.
See table 18 below.
Bit [3] - Phase Detector Delay: When set, this bit enables the delay function.
Bit [2] – PLL Dithering: When set, this bit disables dithering. Dithering reduces the noise error when
calculating the fractional-N synthesizer code. When clear, dithering is enabled and settle time is
increased slightly.
Bit [1] – Not Used: Write a ‘1’.
Bit [0] – PLL Bandwidth: When set, this bit increases the PLL bandwidth slightly to accommodate
higher data rates above 90kbps. When clear, the PLL bandwidth is reduced which allows for faster
settling and reduced phase noise resulting in better RX performance. See Table 19 below.
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Bit
15
1
Bit
14
1
•
•
•
•
•
Bit
13
Output Clock buffer slew rate
Crystal start-up time
Phase Detector Delay (PDD)
PLL Dithering
PLL Bandwidth
0
Bit
12
Email: [e-mail]
0
Bit
11
1
Bit
10
1
Data Rate
<90 kbps
>90 kbps
[POR=CC67h]
Bit
9
0
<2.5 MHz
>5 MHz
Time
3 MHz
2 ms
1ms
Freq
Bit
8
0
Bit
7
0
Table 17.
Table 18.
Table 19.
Phase Noise
-107 dBc/Hz
-102 dBc/Hz
Current
620uA
460uA
BUF1
BUF1
0
0
1
Bit
6
BUF0
BUF0
Bit
XSU
5
X
0
1
0
1
XSU
PLLBW
Bit
4
0
1
PDD
Bit
3
DITH
Bit
2
Bit
1
1
TRC102 - 4/8/08
Page 42 of 51
PLLBW
Bit
0