E-STLC2500C ST-Ericsson Inc, E-STLC2500C Datasheet

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E-STLC2500C

Manufacturer Part Number
E-STLC2500C
Description
BLUETOOTH EDR SGL CHIP 48WFBGA
Manufacturer
ST-Ericsson Inc
Series
STLC2500r
Datasheet

Specifications of E-STLC2500C

Frequency
2.4GHz
Modulation Or Protocol
Bluetoothv2.0+EDR
Power - Output
8dBm
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Package / Case
48-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-
Operating Temperature
-
Applications
-
Sensitivity
-
Memory Size
-
Data Rate - Maximum
-
Current - Transmitting
-
Current - Receiving
-

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Features
January 2006
For further information contact your local STMicroelectronics sales office.
The lowest power consumption by design and
technology (see
World best EDR throughput (see
World most performing BT-WLAN coexistence
support for several BT/WLAN coexistence
algorithms (i.e. 2/3/4-wire PTA, in a very
flexible and parametrical way to optimize voice
and data quality over Bluetooth and WLAN)
Superior voice quality
– Pitch-Period Error Concealment (PPEC) for
Extended range
– Tx output power up to 8 dBm
Pre-calibrated RF
– Auto calibration (VCO, filters), no RF
Bluetooth™V2.0 + EDR compliant
– Full EDR support and all BT1.2 errata
– All EDR data rates and packet types
Backward compatibility with legacy devices
through extended V1.2 feature support
– Adaptive Frequency Hopping (AFH)
– Faster connections through interlaced scan
– Extended SCO (eSCO) links
Point-to-point, point-to-multi-point
(up to 7 slaves) and scatternet capability
Asynchronous Connection-Less (ACL) logical
transport link
Synchronous Connection Oriented (SCO) link
for 2 simultaneous SCO channels at 64Kbps
Clock support for all cellular standards: system
clock input and low power clock
ARM7TDMI CPU with 32-bit core and AMBA
(AHB-APB) bus configuration
Patch RAM capability
improved speech quality (in the vicinity of
interference)
calibration required in production
Table 1
)
Table 1
)
Rev 1
Description
The STLC2500C is a single chip ROM-based
Bluetooth solution implemented in 0.13 µm ultra
low power, ultra low leakage CMOS technology
for mobile terminal applications requiring
integration up to HCI level. Patch RAM is
available, enabling multiple patches/upgrades.
The STLC2500C offers multiple interface options.
The radio has been designed specifically for
single chip requirements for minimal consumption
and BOM count.
On-chip RAM, on-chip ROM
Communication interfaces
– Fast UART up to 4Mbps for HCI
– SPI interface up to 6 Mbps for HCI
– PCM interface for voice
– WirelessLAN coexistence with 2, 3, 4 wires
– 19 programmable GPIOs
– Fast master I2C interface
Ciphering support up to 128-bit keys
Software support up to HCI stack
– H4 and H5 HCI transport layer
– HCI proprietary commands and single HCI
Internal power management
Supports 1.65V to 2.85 Volts IO systems
Seven external components: six decoupling
capacitors and one single antenna interface
Ultra low power architecture with 3 different low
power modes: sleep , deep sleep and
complete power down
Bluetooth
command for patch/upgrade download
WFBGA48 (4.5mm x 4.5 mmx 0.8 mm)
TM
EDR Single Chip
STLC2500C
DATA BRIEF
www.st.com
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E-STLC2500C Summary of contents

Page 1

... ARM7TDMI CPU with 32-bit core and AMBA (AHB-APB) bus configuration ■ Patch RAM capability January 2006 For further information contact your local STMicroelectronics sales office. Bluetooth WFBGA48 (4.5mm x 4.5 mmx 0.8 mm) Table 1 ) ■ On-chip RAM, on-chip ROM ■ ...

Page 2

... Applications ■ Mobile terminal platforms Order codes Part Number E-STLC2500C E-STLC2500CTR WFBGA48 Figure 1. Block diagram Table 1. Technical specifications Parameter Power consumption Audio communication Data communication at maximum throughput Complete power down Data rate throughput at host interface in EDR mode 2/4 Package Packing WFBGA48 ...

Page 3

... STLC2500C Revision history Table 2. Document revision history Date 29-Jan-2006 Revision 1 Initial release. Rev 1 Changes 3/4 ...

Page 4

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