ATMEGA2561R212-AU Atmel, ATMEGA2561R212-AU Datasheet - Page 339
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ATMEGA2561R212-AU
Manufacturer Part Number
ATMEGA2561R212-AU
Description
BUNDLE ATMEGA2561/RF212 TQFP
Manufacturer
Atmel
Datasheet
1.ATMEGA640V-8CU.pdf
(444 pages)
Specifications of ATMEGA2561R212-AU
Frequency
800MHz, 900MHz
Modulation Or Protocol
802.15.4 Zigbee, 6LoWPAN, ISM
Data Interface
PCB, Surface Mount
Memory Size
256kB Flash, 4kB EEPROM, 8kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
64-TQFP, 32-QFN
Processor Series
ATMEGA256x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
256 KB
Data Ram Size
8 KB
Development Tools By Supplier
ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-
Power - Output
-
Operating Temperature
-
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Transmitting
-
Current - Receiving
-
Lead Free Status / Rohs Status
Details
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29.6.1
2549M–AVR–09/10
Signal Names
In this section, some pins of the ATmega640/1280/1281/2560/2561 are referenced by signal
names describing their functionality during parallel programming, see
9. Pins not described in the following table are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.
The bit coding is shown in
When pulsing WR or OE, the command loaded determines the action executed. The different
commands are shown in
Figure 29-1. Parallel Programming
Note:
Table 29-9.
Programming Mode
Signal Name in
RDY/BSY
Unused Pins should be left floating.
PAGEL
DATA
BS1
XA0
XA1
BS2
WR
OE
Pin Name Mapping
Table 29-13 on page
RDY/BSY
Pin Name
Table 29-12 on page
PAGEL
PB7-0
+12V
PD1
PD2
PD3
PD4
PD5
PD6
PD7
BS1
XA0
XA1
BS2
PA0
WR
OE
ATmega640/1280/1281/2560/2561
(Note:)
I/O
I/O
PD1
PD2
PD3
PD4
PD5
PD6
PD7
RESET
XTAL1
GND
O
PA0
I
I
I
I
I
I
I
Program Memory and EEPROM data Page Load.
Bi-directional Data bus (Output when OE is low).
Function
0: Device is busy programming, 1: Device is ready for
new command.
Output Enable (Active low).
Write Pulse (Active low).
Byte Select 1.
XTAL Action Bit 0
XTAL Action Bit 1
Byte Select 2.
340.
340.
PB7 - PB0
AVCC
VCC
+5V
+5V
DATA
Figure 29-1
and
Table 29-
339
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