ATMEGA2561R212-MU Atmel, ATMEGA2561R212-MU Datasheet - Page 224
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
ATMEGA2561R212-MU
Manufacturer Part Number
ATMEGA2561R212-MU
Description
BUNDLE ATMEGA2561/RF212 QFN
Manufacturer
Atmel
Datasheet
1.ATMEGA640V-8CU.pdf
(444 pages)
Specifications of ATMEGA2561R212-MU
Frequency
800MHz, 900MHz
Modulation Or Protocol
802.15.4 Zigbee, 6LoWPAN, ISM
Data Interface
PCB, Surface Mount
Memory Size
256kB Flash, 4kB EEPROM, 8kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
64-QFN, 32-QFN
Processor Series
ATMEGA256x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
256 KB
Data Ram Size
8 KB
Development Tools By Supplier
ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-
Power - Output
-
Operating Temperature
-
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Transmitting
-
Current - Receiving
-
Lead Free Status / Rohs Status
Details
- Current page: 224 of 444
- Download datasheet (10Mb)
21.9.3
2549M–AVR–09/10
UCSRnB – USART Control and Status Register n B
• Bit 3 – DORn: Data OverRun
This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive
buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a
new start bit is detected. This bit is valid until the receive buffer (UDRn) is read. Always set this
bit to zero when writing to UCSRnA.
• Bit 2 – UPEn: USART Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when received and the
Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer
(UDRn) is read. Always set this bit to zero when writing to UCSRnA.
• Bit 1 – U2Xn: Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when using syn-
chronous operation.
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou-
bling the transfer rate for asynchronous communication.
• Bit 0 – MPCMn: Multi-processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCMn bit is written to
one, all the incoming frames received by the USART Receiver that do not contain address infor-
mation will be ignored. The Transmitter is unaffected by the MPCMn setting. For more detailed
information see
• Bit 7 – RXCIEn: RX Complete Interrupt Enable n
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt
will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the RXCn bit in UCSRnA is set.
• Bit 6 – TXCIEn: TX Complete Interrupt Enable n
Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt
will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the TXCn bit in UCSRnA is set.
• Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n
Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will
be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written
to one and the UDREn bit in UCSRnA is set.
• Bit 4 – RXENn: Receiver Enable n
Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper-
ation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FEn, DORn, and UPEn Flags.
Bit
Read/Write
Initial Value
RXCIEn
R/W
“Multi-processor Communication Mode” on page
7
0
TXCIEn
R/W
6
0
ATmega640/1280/1281/2560/2561
UDRIEn
R/W
5
0
RXENn
R/W
4
0
TXENn
R/W
3
0
UCSZn2
R/W
2
0
221.
RXB8n
R
1
0
TXB8n
R/W
0
0
UCSRnB
224
Related parts for ATMEGA2561R212-MU
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![ATMEGA2561](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
ATMEL Corporation
Datasheet:
![ATMEGA2561-16MU](/photos/12/13/121326/313-64-qfn_tmb.jpg)
Part Number:
Description:
IC AVR MCU 256K 16MHZ 64-QFN
Manufacturer:
Atmel
Datasheet:
![ATMEGA2561-16AU](/photos/12/13/121332/313-64-tqfp_tmb.jpg)
Part Number:
Description:
IC AVR MCU 256K 16MHZ 64TQFP
Manufacturer:
Atmel
Datasheet:
![ATMEGA2561-16MI](/photos/12/13/121326/313-64-qfn_tmb.jpg)
Part Number:
Description:
IC AVR MCU 256K 16MHZ 64-QFN
Manufacturer:
Atmel
Datasheet:
![ATMEGA2561-16AUR](/images/manufacturer_photos/0/0/78/atmel_tmb.jpg)
Part Number:
Description:
MCU AVR 256K FLASH 16MHZ 44TQFP
Manufacturer:
Atmel
Datasheet:
![ATMEGA2561-16MUR](/images/manufacturer_photos/0/0/78/atmel_tmb.jpg)
Part Number:
Description:
MCU AVR 256K FLASH 16MHZ 44QFN
Manufacturer:
Atmel
Datasheet:
![ATMEGA2561-16AI](/photos/12/13/121332/313-64-tqfp_tmb.jpg)
Part Number:
Description:
IC AVR MCU 256K 16MHZ 64TQFP
Manufacturer:
Atmel
Datasheet:
![ATSTK600](/photos/9/20/92038/atstk600_tmb.jpg)
Part Number:
Description:
DEV KIT FOR AVR/AVR32
Manufacturer:
Atmel
Datasheet:
![U641B](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
INTERVAL AND WIPE/WASH WIPER CONTROL IC WITH DELAY
Manufacturer:
ATMEL Corporation
Datasheet:
![U4082B](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
Low-Voltage Voice-Switched IC for Hands-Free Operation
Manufacturer:
ATMEL Corporation
Datasheet:
![U4089B](/images/manufacturer_photos/0/0/79/atmel_corporation_tmb.jpg)
Part Number:
Description:
MONOLITHIC INTEGRATED FEATUREPHONE CIRCUIT
Manufacturer:
ATMEL Corporation
Datasheet: