ATMEGA2561R231-MU Atmel, ATMEGA2561R231-MU Datasheet - Page 162
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ATMEGA2561R231-MU
Manufacturer Part Number
ATMEGA2561R231-MU
Description
BUNDLE ATMEGA2561/RF231 QFN
Manufacturer
Atmel
Datasheet
1.ATMEGA640V-8CU.pdf
(444 pages)
Specifications of ATMEGA2561R231-MU
Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee, 6LoWPAN, RF4CE, SP100, WirelessHART™, ISM
Data Interface
PCB, Surface Mount
Memory Size
256kB Flash, 4kB EEPROM, 8kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
64-QFN, 32-QFN
Processor Series
ATMEGA256x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
256 KB
Data Ram Size
8 KB
Development Tools By Supplier
ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-
Power - Output
-
Operating Temperature
-
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Transmitting
-
Current - Receiving
-
Lead Free Status / Rohs Status
Details
- Current page: 162 of 444
- Download datasheet (10Mb)
16.11.10 TCCR3C – Timer/Counter 3 Control Register C
16.11.11 TCCR4C – Timer/Counter 4 Control Register C
16.11.12 TCCR5C – Timer/Counter 5 Control Register C
16.11.13 TCNT1H and TCNT1L – Timer/Counter 1
16.11.14 TCNT3H and TCNT3L – Timer/Counter 3
2549M–AVR–09/10
•
•
•
The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM
mode. When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare
match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed
according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are imple-
mented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the
effect of the forced compare.
A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear
Timer on Compare Match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB/FOCnB bits are always read as zero.
• Bit 4:0 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be written to zero when TCCRnC is written.
Bit
(0x92)
Read/Write
Initial Value
Bit
(0xA2)
Read/Write
Initial Value
Bit
(0x122)
Read/Write
Initial Value
Bit
(0x85)
(0x84)
Read/Write
Initial Value
Bit
(0x95)
(0x94)
Read/Write
Initial Value
Bit 7 – FOCnA: Force Output Compare for Channel A.
Bit 6 – FOCnB: Force Output Compare for Channel B.
Bit 5 – FOCnC: Force Output Compare for Channel C.
FOC3A
FOC4A
FOC5A
R/W
R/W
W
W
W
7
0
7
0
7
0
7
0
7
0
FOC3B
FOC4B
FOC5B
R/W
R/W
W
W
W
6
0
6
0
6
0
6
0
6
0
ATmega640/1280/1281/2560/2561
FOC3C
FOC4C
FOC3C
R/W
R/W
W
W
W
5
0
5
0
5
0
5
0
5
0
R/W
R/W
R
R
R
4
–
0
4
–
0
4
–
0
4
0
4
0
TCNT1[15:8]
TCNT3[15:8]
TCNT1[7:0]
TCNT3[7:0]
R/W
R/W
R
R
R
3
0
3
0
3
–
0
3
–
0
3
–
0
R/W
R/W
2
0
2
0
R
R
R
2
–
0
2
–
0
2
–
0
R/W
R/W
R
R
R
1
0
1
0
1
0
1
0
1
0
–
–
–
R/W
R/W
R
R
R
0
0
0
0
0
–
0
0
–
0
0
–
0
TCCR3C
TCCR4C
TCCR5C
TCNT1H
TCNT1L
TCNT3H
TCNT3L
162
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