SI1010-A-GM Silicon Laboratories Inc, SI1010-A-GM Datasheet - Page 220
![IC TXRX MCU + EZRADIOPRO](/photos/14/21/142131/42-qfn-series_sml.jpg)
SI1010-A-GM
Manufacturer Part Number
SI1010-A-GM
Description
IC TXRX MCU + EZRADIOPRO
Manufacturer
Silicon Laboratories Inc
Specifications of SI1010-A-GM
Package / Case
42-QFN
Frequency
240MHz ~ 960MHz
Data Rate - Maximum
256kbps
Modulation Or Protocol
FSK, GFSK, OOK
Applications
General Purpose
Power - Output
20dBm
Sensitivity
-121dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
18.5mA
Current - Transmitting
85mA
Data Interface
PCB, Surface Mount
Memory Size
16kB Flash, 768B RAM
Antenna Connector
PCB, Surface Mount
Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
240 MHz to 960 MHz
Interface Type
UART, SMBus, SPI, PCA
Output Power
20 dBm
Operating Supply Voltage
0.9 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Supply Current
4 mA
Minimum Operating Temperature
- 40 C
Modulation
FSK, GFSK, OOK
Protocol Supported
C2, SMBus
Core
8051
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
768 B
Supply Current (max)
4 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1874-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI1010-A-GM
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
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Si1010/1/2/3/4/5
21.1. Port I/O Modes of Operation
Port pins P0.0–P1.6 use the Port I/O cell shown in Figure 21.2. Each Port I/O cell can be configured by
software for analog I/O or digital I/O using the PnMDIN registers. On reset, all Port I/O cells default to a dig-
ital high impedance state with weak pull-ups enabled.
21.1.1. Port Pins Configured for Analog I/O
Any pins to be used as Comparator or ADC input, external oscillator input/output, or AGND, VREF, or Cur-
rent Reference output should be configured for analog I/O (PnMDIN.n = 0). When a pin is configured for
analog I/O, its weak pullup and digital receiver are disabled. In most cases, software should also disable
the digital output drivers. Port pins configured for analog I/O will always read back a value of 0 regardless
of the actual voltage on the pin.
Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins
configured as digital inputs may still be used by analog peripherals; however, this practice is not recom-
mended and may result in measurement errors.
21.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UART, SPI, SMBus, etc.), external digital event capture func-
tions, or as GPIO should be configured as digital I/O (PnMDIN.n = 1). For digital I/O pins, one of two output
modes (push-pull or open-drain) must be selected using the PnMDOUT registers.
Push-pull outputs (PnMDOUT.n = 1) drive the Port pad to the VDD_MCU/DC+ or GND supply rails based
on the output logic value of the Port pin. Open-drain outputs have the high side driver disabled; therefore,
they only drive the Port pad to GND when the output logic value is 0 and become high impedance inputs
(both high and low drivers turned off) when the output logic value is 1.
When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the Port pad to
the VDD_MCU/DC+ supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are
disabled when the I/O cell is driven to GND to minimize power consumption and may be globally disabled
by setting WEAKPUD to 1. The user must ensure that digital I/O are always internally or externally pulled
or driven to a valid logic state. Port pins configured for digital I/O always read back the logic state of the
Port pad, regardless of the output logic value of the Port pin.
220
WEAKPUD
(Weak Pull-Up Disable)
Pn.x – Output
Logic Value
(Port Latch or
Crossbar)
PnMDOUT.x
(1 for push-pull)
(0 for open-drain)
XBARE
(Crossbar
Enable)
Pn.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
To/From Analog
Peripheral
PnMDIN.x
(1 for digital)
(0 for analog)
Figure 21.2. Port I/O Cell Block Diagram
Rev. 1.0
VDD_MCU/DC+
GND
VDD_MCU/DC+
(WEAK)
PORT
PAD
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