EM357-RTR Ember, EM357-RTR Datasheet - Page 182
EM357-RTR
Manufacturer Part Number
EM357-RTR
Description
IC RF TXRX ZIGBEE 192KB 48QFN
Manufacturer
Ember
Specifications of EM357-RTR
Frequency
2.4GHz
Data Rate - Maximum
250kbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
5dBm
Sensitivity
-100dBm
Voltage - Supply
2.1 V ~ 3.6 V
Current - Receiving
26mA
Current - Transmitting
31mA
Data Interface
PCB, Surface Mount
Memory Size
192kB Flash, 12kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
636-1011-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EM357-RTR
Manufacturer:
SILICON
Quantity:
3 000
Part Number:
EM357-RTR
Manufacturer:
SILICON
Quantity:
20 000
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Reset initializes the offset to zero (ADC_OFFSET = 0) and gain factor to one (ADC_GAIN = 0x8000).
10.1.4 DMA
The ADC DMA channel writes converted data, which incorporates the offset/gain correction, into a DMA buffer
in RAM.
The ADC DMA buffer is defined by two registers:
To prepare the DMA channel for operation, reset it by writing the ADC_DMARST bit in the ADC_DMACFG
register, then start the DMA in either linear or auto wrap mode by setting the ADC_DMALOAD bit in the
ADC_DMACFG register. The ADC_DMAAUTOWRAP bit in the ADC_DMACFG register selects the DMA mode: 0 for
linear mode, 1 for auto wrap mode.
When the DMA fills the lower and upper halves of the buffer, it sets the INT_ADCULDHALF and
INT_ADCULDFULL bits, respectively, in the INT_ADCFLAG register. The current location to which the DMA is
writing can also be determined by reading the ADC_DMACUR register.
10.1.5 ADC Configuration Register
The ADC configuration register (ADC_CFG) sets up most of the ADC operating parameters.
10.1.5.1 Input
The analog input of the ADC can be chosen from various sources. The analog input is configured with the
ADC_MUXP and ADC_MUXN bits within the ADC_CFG register. Table 10-2 shows the possible input selections.
ADC_DMABEG is the start address of the buffer and must be even.
ADC_DMASIZE specifies the size of the buffer in 16-bit samples, or half its length in bytes.
In linear mode the DMA writes to the buffer until the number of samples given by ADC_DMASIZE has been
output. The DMA then stops and sets the INT_ADCULDFULL bit in the INT_ADCFLAG register. If another ADC
conversion completes before the DMA is reset or the ADC is disabled, the INT_ADCOVF bit in the
INT_ADCFLAG register is set.
In auto wrap mode the DMA writes to the buffer until it reaches the end, then resets its pointer to the
start of the buffer and continues writing samples. The DMA transfers continue until the ADC is disabled or
the DMA is reset.
Final
10-3
EM351 / EM357
120-035X-000G
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